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Displaying 1-24 out of 24 total
A low-cost fault-tolerant technique for Carry Look-Ahead adder
Found in: On-Line Testing Symposium, IEEE International
By Alireza Namazi, Yasser Sedaghat, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:June 2009
pp. 217-222
This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bi...
 
A High Speed and Low Cost Error Correction Technique for the Carry Select Adder
Found in: Availability, Reliability and Security, International Conference on
By Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:March 2009
pp. 635-640
In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error ...
 
Feedback-Based Energy Management in a Standby-Sparing Scheme for Hard Real-Time Systems
Found in: Real-Time Systems Symposium, IEEE International
By Mohammad Khavari Tavana,Mohammad Salehi,Alireza Ejlali
Issue Date:December 2011
pp. 349-356
The interaction between fault tolerance and energy consumption is an interesting avenue in the realm of designing embedded systems. In this paper, a scheme for reducing energy consumption in conventional standby-sparing systems is introduced. In the propos...
 
A Comparative Study of System-Level Energy Management Methods for Fault-Tolerant Hard Real-Time Systems
Found in: IEEE Transactions on Computers
By Soheil Aminzadeh,Alireza Ejlali
Issue Date:September 2011
pp. 1288-1299
Low energy consumption and fault tolerance are often key objectives in the design of real-time embedded systems. However, these objectives are at odds, and there is a trade-off between them. Real-time systems usually use system level energy reduction metho...
 
Schedule Swapping: A Technique for Temperature Management of Distributed Embedded Systems
Found in: Embedded and Ubiquitous Computing, IEEE/IFIP International Conference on
By Farzad Samie Ghahfarokhi, Alireza Ejlali
Issue Date:December 2010
pp. 1-6
A distributed embedded system consists of different processing elements (PEs) communicating via communication links. PEs have various power characteristics and in turn, have different thermal profiles. With new technologies, processor power density is dram...
 
A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-Immunity
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Mehrdad Khatir, Alireza Ejlali
Issue Date:July 2010
pp. 195-200
Charge recovery is a promising concept to design (cryptographic) VLSI circuits with low energy dissipation. However, unsatisfactory designs of proposed logic cells degrade its theoretical efficiency significantly both in its energy consumption and the resi...
 
Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies
Found in: Availability, Reliability and Security, International Conference on
By Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:March 2009
pp. 448-453
This paper presents a fault tolerant and energy efficient write-back set-associative cache, which has a heterogeneous structure. The cache architecture is based on partitioning the ways of each set into two different parts. In each set, one cache way uses ...
 
A Micro-FT-UART for Safety-Critical SoC-Based Applications
Found in: Availability, Reliability and Security, International Conference on
By Mohammad-Hamed Razmkhah, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:March 2009
pp. 316-321
This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors....
 
Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off
Found in: Quality Electronic Design, International Symposium on
By Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:March 2009
pp. 839-844
Write-through caches potentially have higher reliability than write-back caches. However, write-back caches are more energy efficient. This paper provides a comparison between the write-back and write-through policies based on the combination of reliabilit...
 
A Low Power Error Detection Technique for Floating-Point Units in Embedded Applications
Found in: Embedded and Ubiquitous Computing, IEEE/IFIP International Conference on
By Seyed Mohammad Hossein Shekarian, Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:December 2008
pp. 199-205
Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the r...
 
Control-Flow Checking Using Branch Instructions
Found in: Embedded and Ubiquitous Computing, IEEE/IFIP International Conference on
By Mostafa Jafari-Nodoushan, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:December 2008
pp. 66-72
This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and i...
 
An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Hamed Tabkhi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:October 2008
pp. 445-453
This paper presents a checkpointing scheme for rollback error recovery, called Asymmetric Checkpointing and Rollback Recovery (ACRR) which stores the processor states in an asymmetric manner. In this way, error recovery latency and the number of checkpoint...
 
A secure and low-energy logic style using charge recovery approach
Found in: Low Power Electronics and Design, International Symposium on
By Mehrdad Khatir, Amir Moradi, Alireza Ejlali, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh
Issue Date:August 2008
pp. 259-264
The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high ener...
 
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
Found in: Networks-on-Chip, International Symposium on
By Alireza Ejlali, Bashir M. Al-Hashimi
Issue Date:April 2008
pp. 67-76
Pipelined on-chip interconnects are used in on-chip networks to increase the throughput of interconnects and to achieve freedom in choosing arbitrary network topologies. Since reliability and energy consumption are prominent issues in on-chip networks, the...
 
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali
Issue Date:March 2004
pp. 327-332
The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs u...
 
Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems
Found in: Parallel and Distributed Computing, International Symposium on
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:October 2003
pp. 281
This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial ...
 
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation
Found in: Dependable Systems and Networks, International Conference on
By Alireza Ejlali, Seyed Ghassem Miremadi, Hamidreza Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
Issue Date:June 2003
pp. 479
This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a...
 
Switch-Level Emulation
Found in: Design Automation Conference
By Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:June 2003
pp. 644
This paper presents a method for the fast emulation of switch-level circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped ...
 
Switch-level emulation
Found in: Proceedings of the 40th conference on Design automation (DAC '03)
By Alireza Ejlali, Ejlali Ghassem Miremadi
Issue Date:June 2003
pp. 644-649
This paper presents a method for the fast emulation of switch-level circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped ...
     
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:November 2003
pp. 485
This paper presents a fault injection tool, called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent ...
 
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Found in: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis (CODES+ISSS '09)
By Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles
Issue Date:October 2009
pp. 193-202
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redundancy is generally more preferable than hardware redundancy. However, hard re...
     
A secure and low-energy logic style using charge recovery approach
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Alireza Ejlali, Amir Moradi, Mahmoud Salmasizadeh, Mehrdad Khatir, Mohammad T. Manzuri Shalmani
Issue Date:August 2008
pp. 383-384
The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high ener...
     
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Alireza Ejlali, Bashir M. Al-Hashimi, Paul Rosinger, Seyed Ghassem Miremadi
Issue Date:April 2007
pp. 1647-1652
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the various trade-offs between two of these objectives. However, as we will argue la...
     
Cache size selection for performance, energy and reliability of time-constrained systems
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Sudhakar M. Reddy, Yuan Cai
Issue Date:January 2006
pp. 923-928
Improving performance, reducing energy consumption and enhancing reliability are three important objectives for embedded computing systems design. In this paper, we study the joint impact of cache size selection on these three objectives. For this purpose,...
     
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