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Displaying 1-11 out of 11 total
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance
Found in: Design Automation Conference
By Janusz Rajski, Mark Kassab, Aiman El-Maleh
Issue Date:June 1998
pp. 625-631
This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve ...
 
Testability Implications of Performance-Driven Logic Synthesis
Found in: IEEE Design and Test of Computers
By Thomas E. Marchok, Aiman El-Maleh, Janusz Rajski, Wojciech Maly
Issue Date:June 1995
pp. 32-39
With the growth in IC manufacturing costs, an understanding of the effects of more sophisticated logic synthesis techniques is essential for future advances in both the theory and implementation of automatic circuit synthesis. This article is a summary of ...
 
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
Found in: VLSI Test Symposium, IEEE
By Aiman El-Maleh, Khaled Al-Utaibi
Issue Date:May 2003
pp. 179
Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and co...
 
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
Found in: VLSI Test Symposium, IEEE
By Aiman El-Maleh, Ali Al-Suwaiyan
Issue Date:May 2002
pp. 0053
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compactio...
 
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement
Found in: Computer Design, International Conference on
By Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman El-Maleh
Issue Date:September 2001
pp. 0484
Abstract: In this paper, we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI standard cell placement targeting low power dissipation and high performance. Due to the imprecise nature of design information at the placement s...
 
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
Found in: VLSI Test Symposium, IEEE
By Aiman El-Maleh, Esam Khan, Saif al Zahir
Issue Date:April 2001
pp. 0054
The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and very efficient lossless compression technique for testing sys...
 
A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC)
Found in: International Conference on Computer Supported Cooperative Work in Design
By Wenfa Zhan, Aiman El-Maleh
Issue Date:April 2009
pp. 21-25
A new scheme of test data compression, namely equal-run-length coding (ERLC) scheme is presented, which is based on run-length. It first considers both types of runs of 0's and 1's, then it further explores the relationship between two consecutive runs on ...
 
Using input/output queues to increase LDPC decoder performance
Found in: Computer Systems and Applications, ACS/IEEE International Conference on
By Esa Alghonaim, Aiman El-Maleh, M. Adnan Landolsi
Issue Date:April 2008
pp. 304-308
The paper presents a novel approach to increase the performance and/or throughput of iterative belief propagation (BP) decoding of low density parity check (LDPC) codes. The proposed approach is based on utilizing the decoder idle time by introducing two q...
 
On Test Set Preservation of Retimed Circuits
Found in: Design Automation Conference
By Janusz Rajski, Thomas Marchok, Wojciech Maly, Aiman El-Maleh
Issue Date:June 1995
pp. 176-182
Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that retim...
 
A fast sequential learning technique for real circuits with application to enhancing ATPG performance
Found in: Proceedings of the 35th annual conference on Design automation conference (DAC '98)
By Aiman El-Maleh, Janusz Rajski, Mark Kassab
Issue Date:June 1998
pp. 625-631
This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve ...
     
On test set preservation of retimed circuits
Found in: Proceedings of the 32nd ACM/IEEE conference on Design automation conference (DAC '95)
By Aiman El-Maleh, Janusz Rajski, Thomas Marchok, Wojciech Maly
Issue Date:June 1995
pp. 176-182
A new gridless router accelerated by Content Addressable Memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based acceler...
     
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