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Displaying 1-7 out of 7 total
T2: Statistical Methods for VLSI Test and Burn-in Optimization
Found in: Asian Test Symposium
By Adit Singh
Issue Date:December 2005
pp. xxx
VLSI circuits have been traditionally tested individually following manufacture; the same tests being applied to all ICs. However, as manufacturing test costs continue to show a disproportionate increase in relation to IC fabrication costs, innovative new ...
SSTKR: Secure and Testable Scan Design through Test Key Randomization
Found in: Asian Test Symposium
By Mohammed Abdul Razzaq,Virendra Singh,Adit Singh
Issue Date:November 2011
pp. 60-65
Scan test is the standard method, practiced by industry, that has consistently provided high fault coverage due to high controllability and high observability. The scan chain allows to control and observe the internal signals of a chip. However, this prope...
Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience
Found in: 2014 27th International Conference on VLSI Design
By Jayaram Natarajan,Sahil Kapoor,Debesh Bhatta,Abhijit Chatterjee,Adit Singh
Issue Date:January 2014
pp. 122-127
Modern microprocessor pipelines experience timing uncertainties due to manufacturing process variations, thermal variations, supply voltage droop and data-dependent path delays. This leads to power and/or performance inefficiencies in current timing guard ...
Special session 4B: Elevator talks
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Jennifer Dworak,Ronald Shawn Blanton,Masahiro Fujita,Kazumi Hatayama,Naghmeh Karimi,Michail Maniatakos,Antonis Paschalis,Adit Singh,Tian Xia
Issue Date:April 2013
pp. 1
Start of the
Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations
Found in: Asian Test Symposium
By Jayaram Natarajan,Joshua Wells,Abhijit Chatterjee,Adit Singh
Issue Date:November 2011
pp. 154-160
Exhaustive speed testing of all the cores under extreme inter and intra-die process variations in a large chip multi processor (CMP) is expensive in terms of test time and may not guarantee full CMP functionality due to lack of coverage of timing failures ...
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
Found in: On-Line Testing Symposium, IEEE International
By Abhijit Chatterjee, Jacob Abraham, Adit Singh, Elie Maricau, Rakesh Kumar, Christos Papachristou
Issue Date:June 2009
pp. 129
There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that erro...
Current testing: Dead or alive?
Found in: 2013 18th IEEE European Test Symposium (ETS)
By Hans Manhaeve,Pete Harrod,Adit Singh,Chintan Patel,Ralf Arnolc,Davide Appello
Issue Date:May 2013
pp. 1
Current, voltage and time (frequency) are the base parameters describing an electronic system. In the 1700's, Benjamin Franklin was one of the first experimenting with current tests, followed by many others shaping the current domain. In 1963 Frank Wanlass...