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Displaying 1-7 out of 7 total
EVAL: Utilizing processors with variation-induced timing errors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas
Issue Date:November 2008
pp. 423-434
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case parameter values, we may lose substantial performance. An alternate approach expl...
 
Facelift: Hiding and slowing down aging in multicores
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Abhishek Tiwari, Josep Torrellas
Issue Date:November 2008
pp. 129-140
Processors progressively age during their service life due to normal workload activity. Such aging results in gradually slower circuits. Anticipating this fact, designers add timing guardbands to processors, so that processors last for a number of years. A...
 
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas
Issue Date:December 2007
pp. 27-42
Parameter variation is detrimental to a processor's frequency and leakage power. One proposed technique to mitigate it is Fine-Grain Body Biasing (FGBB), where different parts of the processor chip are given a voltage bias that changes the speed and leakag...
 
Patching Processor Design Errors with Programmable Hardware
Found in: IEEE Micro
By Smruti Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas
Issue Date:January 2007
pp. 12-25
Equipping processors with programmable hardware to patch design errors lets manufacturers release regular hardware patches, avoiding costly chip recalls and potentially speeding time to market. For each error detected, the manufacturer creates a fingerprin...
 
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas
Issue Date:December 2006
pp. 26-37
Although processor design verification consumes ever-increasing resources, many design defects still slip into production silicon. In a few cases, such bugs have caused expensive chip recalls. To truly improve productivity, hardware bugs should be handled ...
 
Estimation of Linear Stochastic Systems over a Queueing Network
Found in: Wireless Technologies/High Speed Networks/Multimedia Communications Systems/Sensor Networks, International Conference on
By Michael Epstein, Abhishek Tiwari, Ling Shi, Richard M. Murray
Issue Date:August 2005
pp. 389-394
In this paper, we consider the standard state estimation problem over a congested packet-based network. The network is modeled as a queue with a single server processing the packets. This provides a framework to consider the effect of packet drops, packet ...
 
ReCycle:: pipeline adaptation to tolerate process variation
Found in: Proceedings of the 34th annual international symposium on Computer architecture (ISCA '07)
By Abhishek Tiwari, Josep Torrellas, Smruti R. Sarangi
Issue Date:June 2007
pp. 323-334
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by the pipeline. To improve performance, this paper proposes ReCycle, an architec...
     
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