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An I-IP based approach for the monitoring of NBTI effects in SoCs
Found in: On-Line Testing Symposium, IEEE International
By C. Guardiani, A. Shibkov, A. Brambilla, G. Storti Gajani, D. Appello, F. Piazza, P. Bernardi
Issue Date:June 2009
pp. 15-20
In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor V<inf>TH</inf> degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensa...
Design Strategies for ESD Protection in SOC
Found in: System-on-Chip for Real-Time Applications, International Workshop on
By K. Iniewski, V. Axelrad, A. Shibkov, A. Balasinski, M. Syrzycki
Issue Date:July 2004
pp. 210-214
Design strategies for efficient ESD protection in System-on-Chip (SOC) Integrated Circuits are discussed. Various options for power clamp and I/O ESD architectures are considered. Multiple ESD protection circuits with feedback triggering have been analyzed...