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Displaying 1-50 out of 62 total
Denoising simulated EEG signals: A comparative study of EMD, wavelet transform and Kalman filter
Found in: 2013 IEEE 13th International Conference on Bioinformatics and Bioengineering (BIBE)
By Christos I. Salis,Anastasios E. Malissovas,Paschalis A. Bizopoulos,Alexandros T. Tzallas,P. A. Angelidis,Dimitrios G. Tsalikakis
Issue Date:November 2013
pp. 1-4
Electrooculographic (EOG) artefact is one of the most common contaminations of Electroencephalographic (EEG) recordings. The corruption of EEG characteristics from Blinking Artefacts (BAs) affects the results of EEG signal processing methods and also impai...
   
EEG epileptic seizure detection using k-means clustering and marginal spectrum based on ensemble empirical mode decomposition
Found in: 2013 IEEE 13th International Conference on Bioinformatics and Bioengineering (BIBE)
By Paschalis A. Bizopoulos,Dimitrios G. Tsalikakis,Alexandros T. Tzallas,Dimitrios D. Koutsouris,Dimitrios I. Fotiadis
Issue Date:November 2013
pp. 1-4
The detection of epileptic seizures is of primary interest for the diagnosis of patients with epilepsy. Epileptic seizure is a phenomenon of rhythmicity discharge for either a focal area or the entire brain and this individual behavior usually lasts from s...
   
Energy-optimized cooperative relay network over Nakagami-m fading channels
Found in: 2013 IEEE 9th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob)
By Mulugeta K. Fikadu,Paschalis C. Sofotasios,Qimei Cui,Mikko Valkama
Issue Date:October 2013
pp. 414-421
Recently, due to the exponentially increasing overall energy consumption of the wireless networks, much attention has been directed to the energy efficiency metrics and minimization of energy consumption, both in battery powered terminal devices as well as...
   
Special session 4B: Elevator talks
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Jennifer Dworak,Ronald Shawn Blanton,Masahiro Fujita,Kazumi Hatayama,Naghmeh Karimi,Michail Maniatakos,Antonis Paschalis,Adit Singh,Tian Xia
Issue Date:April 2013
pp. 1
Start of the
 
Low Energy Online Self-Test of Embedded Processors in Dependable WSN Nodes
Found in: IEEE Transactions on Dependable and Secure Computing
By Andreas Merentitis,Nektarios Kranitis,Antonis Paschalis,Dimitris Gizopoulos
Issue Date:January 2012
pp. 86-100
Wireless Sensor Network (WSN) nodes are often deployed in harsh environments where the possibility of permanent and especially intermittent faults due to environmental hazards is significantly increased, while silicon aging effects are also exacerbated. Th...
 
A software-based self-test methodology for in-system testing of processor cache tag arrays
Found in: On-Line Testing Symposium, IEEE International
By G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos
Issue Date:July 2010
pp. 159-164
Software-Based Self-Test (SBST) has emerged as an effective alternative for processor manufacturing and in-system testing. For small memory arrays that lack BIST circuitry such as cache tag arrays, SBST can be a flexible and low-cost solution for March tes...
 
SBST for on-line detection of hard faults in multiprocessor applications under energy constraints
Found in: On-Line Testing Symposium, IEEE International
By A. Merentitis, D. Margaris, N. Kranitis, A. Paschalis, D. Gizopoulos
Issue Date:July 2010
pp. 62-67
Software-Based Self-Test (SBST) has emerged as an effective method for on-line testing of processors integrated in non safety-critical systems. However, especially for multi-core processors, the notion of dependability encompasses not only high quality on-...
 
Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors
Found in: IEEE Transactions on Computers
By Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis
Issue Date:December 2009
pp. 1682-1694
Software-based or instruction-based self-testing has recently emerged as an effective alternative for the manufacturing and online testing of microprocessors, and is progressively adopted by major microprocessor manufacturers mainly as a supplement to othe...
 
An Input Vector Monitoring Concurrent BIST scheme exploiting
Found in: On-Line Testing Symposium, IEEE International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis
Issue Date:June 2009
pp. 206-207
Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent T...
 
Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors
Found in: European Test Symposium, IEEE
By Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Ishwar Parulkar
Issue Date:May 2009
pp. 33-38
Major microprocessor vendors have integrated functional software-based self-testing in their manufacturing test flows during the last decade. Functional self-testing is performed by test programs that the processor executes at-speed from on-chip memory. Mu...
 
Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units
Found in: IEEE Transactions on Dependable and Secure Computing
By George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis
Issue Date:April 2009
pp. 124-134
Online periodic testing of microprocessors is a valuable means to increase the reliability of a low-cost system, when neither hardware nor time redundant protection schemes can be applied. This is particularly valid for floating-point (FP) units, which are...
 
Functional self-testing for bus-based symmetric multiprocessors
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By A. Apostolakis, A. Paschalis, D. Gizopoulos, M. Psarakis
Issue Date:March 2008
pp. 1-30
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first...
     
An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set
Found in: IEEE Transactions on Computers
By Ioannis Voyiatzis, Antonis Paschalis, Dimitris Gizopoulos, Constantin Halatsis, Frosso S. Makri, Miltiadis Hatzimihail
Issue Date:August 2008
pp. 1012-1022
Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of o...
 
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Apostolakis, D. Gizopoulos, M. Psarakis, A. Paschalis
Issue Date:March 2008
pp. 1304-1309
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first...
 
Hybrid-SBST Methodology for Efficient Testing of Processor Cores
Found in: IEEE Design and Test of Computers
By Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis Paschalis, Dimitris Gizopoulos
Issue Date:January 2008
pp. 64-75
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of embedded processors in SoCs. SBST is a nonintrusive approach that has the potential to provide high-quality at-speed testing at virtually zero pe...
 
On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis
Issue Date:September 2007
pp. 379-397
On-line periodic testing of microprocessors is a viable low-cost alternative for a wide variety of embedded systems which cannot afford hardware or software redundancy techniques but necessitate the detection of intermittent or permanent faults. Low-cost, ...
 
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs
Found in: On-Line Testing Symposium, IEEE International
By A. Apostolakis, M. Psarakis, D. Gizopoulos, A. Paschalis
Issue Date:July 2007
pp. 271-276
Functional Software-Based Self-Testing (SBST) of mi-croprocessors and processor-based testing of Systems-on-Chip (SoCs) have recently attracted the attention of test technology research community because they provide an effective alternative to other tradi...
 
A New Hardware Module for Stereo Matching Using Zernike Moments
Found in: Autonomic and Autonomous Systems, International Conference on
By Paschalis Gonidis, Leonidas Kotoulas, Ioannis Andreadis
Issue Date:June 2007
pp. 33
This paper presents a new hardware module suitable for matching point features between two uncalibrated images of a scene with real-time response. A robust matching is established under a mixed geometric and moment-based correspondence strength function. I...
 
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Found in: European Test Symposium, IEEE
By A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos
Issue Date:May 2007
pp. 111-116
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the most popular applications falling in this category are the various mobile devic...
 
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
Found in: IEEE Transactions on Computers
By George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis
Issue Date:November 2006
pp. 1449-1457
High-speed datapaths in microprocessors and embedded processors contain complex floating-point (FP) arithmetic units which have a critical role in the processor's performance. Although the FP units' complex structure consists of classic integer arithmetic ...
 
Systematic software-based self-test for pipelined processors
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Anand Raghunathan, Antonis Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Srivaths Ravi
Issue Date:July 2006
pp. 393-398
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the...
     
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis
Issue Date:July 2006
pp. 235-241
In this paper, we introduce a fully automated low cost hardware/software platform for efficiently performing fault emulation experiments targeting SEUs in the configuration bits of FPGA devices, without the need for expensive radiation experiments. We prop...
 
Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications
Found in: Design, Automation and Test in Europe Conference and Exhibition
By N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos, C. Halatsis
Issue Date:March 2006
pp. 21
Today's nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability failures that are manifested in the field during the semiconductor product operatio...
 
A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set
Found in: Test Conference, International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis, C. Halatsis
Issue Date:November 2005
pp. 8 pp.-1125
Manufacturing testing is carried-out once in order to ensure the correct operation of the circuit under test right after fabrication, while either periodic off-line testing or concurrent on-line testing is carried-out in order to ensure that the circuit un...
 
Software-Based Self-Test for Pipelined Processors: A Case Study
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By M. Hatzimihail, M. Psarakis, G. Xenoulis, D. Gizopoulos, A. Paschalis
Issue Date:October 2005
pp. 535-543
<p>Software-Based Self-Test (SBST) for processors and processor-based systems recently captured the interest of test technology researchers and practitioners due to its several advantages over traditional hardware Built-In Self-Test (BIST). In this p...
 
Accumulator-Based Weighted Pattern Generation
Found in: On-Line Testing Symposium, IEEE International
By I. Voyiatzis, D. Gizopoulos, A. Paschalis
Issue Date:July 2005
pp. 215-220
<p>Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in Built in Self Test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 ...
 
Software-Based Self-Testing of Embedded Processors
Found in: IEEE Transactions on Computers
By Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, George Xenoulis
Issue Date:April 2005
pp. 461-475
Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-...
 
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Antonis Paschalis, Dimitris Gizopoulos
Issue Date:February 2004
pp. 10578
<p>Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low-cost embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, softwar...
 
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores
Found in: Test Conference, International
By N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian
Issue Date:October 2003
pp. 431
Embedded processor testing techniques based on the execution of self-test routines, have been recently proposed as an effective alternative to classical hardware Built-In Self Test. Software-based self-testing provides at-speed testing capability and does ...
 
Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores
Found in: On-Line Testing Symposium, IEEE International
By G. Xenoulis, D. Gizopoulos, N. Kranitis, A. Paschalis
Issue Date:July 2003
pp. 149
A comprehensive online test strategy requires both concurrent and non-concurrent fault detection capabilities to guarantee SoCs?s successful normal operation in-field at any level of its life cycle. While concurrent fault detection is mainly achieved by ha...
 
Instruction-Based Self-Testing of Processor Cores
Found in: VLSI Test Symposium, IEEE
By N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian
Issue Date:May 2002
pp. 0223
Instruction-based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper...
 
Effective Software Self-Test Methodology for Processor Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian
Issue Date:March 2002
pp. 0592
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing the testing task of complex Systems-on-Chip (SoC) between s...
 
Deterministic Software-Based Self-Testing of Embedded Processor Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian
Issue Date:March 2001
pp. 0092
Abstract: A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage with...
 
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers
Found in: VLSI Test Symposium, IEEE
By M. Psarakis, A. Paschalis, N. Kranitis, D. Gizopoulos, Y. Zorian
Issue Date:April 2001
pp. 0015
The modified Booth array multiplier is the most ubiquitous multiplier architecture in the datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for Booth array multipliers has never been prop...
 
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Found in: Quality Electronic Design, International Symposium on
By N. Kranitis, M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian
Issue Date:March 2001
pp. 343
Effective Built-In Self-Test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regu...
 
Efficient Visualization of Encoded Fourier Transform Infrared Microscopic Data of Osteoporotic Bone
Found in: Computer-Based Medical Systems, IEEE Symposium on
By Gilberto Zamora, Shuyu Yang, Sunanda Mitra, Margaret Peterson, E. P. Paschalis
Issue Date:March 2001
pp. 0197
Abstract: Fourier Transform Infrared Microspectroscopy of bone slices has become a major research tool to analyze the chemical constitution of calcified structures. Qualitative as well quantitative measures of bone components using this technique have show...
 
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
Found in: IEEE Transactions on Computers
By Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian
Issue Date:October 2000
pp. 1083-1099
<p><b>Abstract</b>—Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more compreh...
 
Power-/Energy Efficient BIST Schemes for Processor Data Paths
Found in: IEEE Design and Test of Computers
By Nektarios Kranitis, Dimitris Gizopoulos, Antonis Paschalis, Mihalis Psarakis, Yervant Zorian
Issue Date:October 2000
pp. 15-28
Power in processing cores (embedded processors, DSPs) is primarily consumed in the datapath part which consists of high activity functional modules. In this paper, we propose low power/energy BIST schemes for datapath architectures built around the most co...
 
Low Power/Energy BIST Scheme for Datapaths
Found in: VLSI Test Symposium, IEEE
By D. Gizopoulos, N. Kranitis, M. Psarakis, A Paschalis, Y. Zorian
Issue Date:May 2000
pp. 23
Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for ...
 
Effective low power BIST for datapaths (poster paper)
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '00)
By A. Paschalis, D. Gizopoulos, M. Psarakis, N. Kranitis, Y. Zorian
Issue Date:March 2000
pp. 757
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
Effective Low Power BIST for Datapaths
Found in: Design, Automation and Test in Europe Conference and Exhibition
By D. Gizopoulos, N. Kranitis, M. Psarakis, A. Paschalis, Y. Zorian
Issue Date:March 2000
pp. 757
Power in processing cores (microprocessors, DSPs) is primarily consumed in the datapath part. Among the datapath functional modules, multipliers consume the largest amount of power due to their size and complexity. We propose a low power BIST scheme for da...
 
An Effective Built-In Self-Test Scheme for Parallel Multipliers
Found in: IEEE Transactions on Computers
By Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian
Issue Date:September 1999
pp. 936-950
<p><b>Abstract</b>—In this paper, an effective Built-In Self-Test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawb...
 
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers
Found in: VLSI Test Symposium, IEEE
By Mihalis Psarakis, Antonis Paschalis, Dimitris Gizopoulos, Yervant Zorian
Issue Date:April 1999
pp. 252
Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper, we present, for first time, a BIST architecture which do...
 
An Effective BIST Architecture for Fast Multiplier Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Paschalis, N. Kranitis, M. Psarakis, D. Gizopoulos, Y. Zorian
Issue Date:March 1999
pp. 117
Wallace tree summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex Ics requ...
 
An effective BIST architecture for fast multiplier cores
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '99)
By A. Paschalis, D. Gizopoulos, M. Psarakis, N. Kranitis, Y. Zorian
Issue Date:January 1999
pp. 28-es
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
R-CBIST: An Effective RAM-based Input Vector Monitoring Concurrent BIST Technique
Found in: Test Conference, International
By I. Voyiatzis, A. Paschalis, D. Nikolos, C. Halatsis
Issue Date:October 1998
pp. 918
In this paper a novel Input Vector Monitoring Concurrent BIST technique based on a RAM (R-CBIST) is presented. This technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware ov...
 
Effective Built-In Self-Test for Booth Multipliers
Found in: IEEE Design and Test of Computers
By Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian
Issue Date:July 1998
pp. 105-111
Module generators provided by library vendors supply chip designers with optimized Booth multipliers which are widely used, as embedded cores, in both general purpose datapath structures and specialized Digital Signal Processors. Testing of such multiplier...
 
An Effective BIST Scheme for Arithmetic Logic Un i t s
Found in: Test Conference, International
By Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian, Mihalis Psarakis
Issue Date:November 1997
pp. 868
Multifunction Arithmetic Log ic Units ( ALUs) that realize complex arithmetic and logic operations (like the operations of the 74X 81 family) are widely used in toda y's complex integrated circuits, such as commercial Microprocessors and Digital Signal Pro...
 
Robust Sequential Fault Testing of Iterative Logic Arrays
Found in: VLSI Test Symposium, IEEE
By Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis
Issue Date:May 1997
pp. 238
Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential fault...
 
A Totally Self-checking 1-out-of-3 Code Error Indicator
Found in: European Design and Test Conference
By Antonis Paschalis, Nikos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis
Issue Date:March 1997
pp. 450
In this paper, an asynchronous TSC 1-out-of-3 (1/3) code error indicator is introduced that memorises erroneous 1/3 code inputs {000, 011, 101, 110, 111} with time duration greater than a discrimination time T. Such an error indicator is used to discrimina...
 
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