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Displaying 1-13 out of 13 total
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
Found in: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
By C. Bolchini,A. Miele,C. Sandionigi,M. Ottavi,S. Pontarelli,A. Salsano,C. Metra,M. Omana,D. Rossi,M. Sonza Reorda,L. Sterpone,M. Violante,S. Gerardin,M. Bagatin,A. Paccagnella
Issue Date:October 2012
pp. 121-125
While the shrinking of minimum dimensions of integrated circuits till tenths of nanometers allows the integration of millions of gates on the single chip, it also implies the growth of the importance of effects that could reduce the reliability of circuits...
 
Impact of Aging Phenomena on Soft Error Susceptibility
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Daniele Rossi,Martin Omaña,Cecilia Metra,Alessandro Paccagnella
Issue Date:October 2011
pp. 18-24
In this paper we address the issue of analyzing the effects of negative bias temperature instability (NBTI) on ICs' soft error susceptibility. We show that NBTI reduces significantly the critical charge of nodes of both combinational and sequential circuit...
 
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts
Found in: On-Line Testing Symposium, IEEE International
By P. Rech, M. Grosso, F. Melchiori, D. Loparco, D. Appello, L. Dilillo, A. Paccagnella, M. Sonza Reorda
Issue Date:July 2010
pp. 29-34
This paper reports and analyzes the results of alpha radiation testing campaigns on an embedded microprocessor manufactured with different standard cell libraries, each one enforcing Design for Manufacturing rules at a specific level. A set of analog simul...
 
Evaluating Alpha-induced soft errors in embedded microprocessors
Found in: On-Line Testing Symposium, IEEE International
By P. Rech, S. Gerardin, A. Paccagnella, P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello
Issue Date:June 2009
pp. 69-74
This paper presents the results of Alpha Single Event Upsets tests of an embedded 8051 microprocessor. Cross sections for the different memory resources (i.e., internal registers, code RAM, and user memory) are reported as well as the error rate for differ...
 
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
Found in: VLSI Test Symposium, IEEE
By D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, M. Sonza Reorda
Issue Date:May 2009
pp. 276-281
This paper proposes an efficient low-cost strategy for collecting data during radiation experiments on Systems-on-Chips (SoCs), exploiting the available on-chip Design for Testability (DfT) structures devised for manufacturing test.The approach combines ha...
 
On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By Niccolò Battezzati, Simone Gerardin, Andrea Manuzzato, Alessandro Paccagnella, Sana Rezgui, Luca Sterpone, Massimo Violante
Issue Date:July 2008
pp. 135-140
Field Programmable Gate Arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are ...
 
Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
Issue Date:September 2007
pp. 79-86
We present an experimental analysis of the sensitivity of SRAM-based FPGAs to alpha particles. We study how the different resources inside the FPGA (LUTs, MUXs, PIPs, etc. ) are affected by alpha-induced SEUs, assessing the cross section for the configurat...
 
Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions
Found in: On-Line Testing Symposium, IEEE International
By M. Bagatin, G. Cellere, S. Gerardin, A. Paccagnella, A. Visconti, S. Beltrami, M. Maccarrone
Issue Date:July 2007
pp. 146-151
We tested a commercial 1Gbit 90nm NAND memory under exposure to a constant flux of heavy ions, aiming to study its behaviour in the space environment. We identified and classified different types of errors under various operating conditions. We observed si...
 
Erratic Effects of Irradiation in Floating Gate Memory Cells
Found in: On-Line Testing Symposium, IEEE International
By G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi
Issue Date:July 2006
pp. 51-56
The information stored in Floating Gate (FG) memory arrays can be degraded by single, high energy, ions. Their first effect is a quick and large charge loss from programmed FGs, largely exceeding that expected based on simple models. The second phenomenon ...
 
Soft Errors induced by single heavy ions in Floating Gate memory arrays
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi
Issue Date:October 2005
pp. 275-284
<p>Single, high-energy ions can induce large charge loss from Floating Gates used as basic storage elements in nonvolatile memory cells. The charge loss greatly exceeds that calculated by using conventional models based on generation and recombinatio...
 
Heavy Ion Effects on Configuration Logic of Virtex FPGAs
Found in: On-Line Testing Symposium, IEEE International
By M. Alderighi, A. Candelori, F. Casini, S. D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, G. R. Sechi
Issue Date:July 2005
pp. 49-53
A heavy ion radiation test has been performed to evaluate the SEU sensitivity of Virtex devices. Differently from previous radiation tests, the one here described specifically addresses configuration logic. Previously unreported failure mechanisms have bee...
 
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
Issue Date:February 2004
pp. 10584
This paper analyses the effects of Single Event Upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools d...
 
Analyzing SEU Effects in SRAM-based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
Issue Date:July 2003
pp. 119
Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memo...
 
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