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Displaying 1-15 out of 15 total
An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By M. Poolakkaparambil,J. Mathew,A.M. Jabir,S.P. Mohanty
Issue Date:August 2012
pp. 141-146
Permanent and temporary transient faults are the main concern in modern very large scale integrated circuits (VLSI). The main reason for such high vulnerability of the modern integrated circuit is their high integration density. Miniaturization of devices ...
 
Multiple Bit Error Detection and Correction in GF Arithmetic Circuits
Found in: Electronic System Design, International Symposium on
By J. Mathew, S. Banerjee, P. Mahesh, D. K. Pradhan, A. M. Jabir, S. P. Mohanty
Issue Date:December 2010
pp. 101-106
This paper presents a design technique for multiple bit error correctable (fault tolerant) polynomial basis (PB) multipliers over GF(2^m). These multipliers are the building blocks in certain types of cryptographic hardware, e.g. the Elliptic Curve Crypto ...
 
C-testable S-box implementation for secure advanced encryption standard
Found in: On-Line Testing Symposium, IEEE International
By H. Rahaman, J. Mathew, A. Jabir, D. K. Pradhan
Issue Date:June 2009
pp. 210-211
We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overh...
 
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection
Found in: On-Line Testing Symposium, IEEE International
By Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
Issue Date:July 2008
pp. 16-21
Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SE...
 
C-testable bit parallel multipliers over GF(2m)
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By A. M. Jabir
Issue Date:January 2008
pp. 1-18
We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2m) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testabili...
     
Single Error Correcting Finite Field Multipliers Over GF(2<i><sup>m</sup></i>)
Found in: VLSI Design, International Conference on
By Jimson Mathew, A. Costas, A.M. Jabir, H. Rahaman, D.K. Pradhan
Issue Date:January 2008
pp. 33-38
designing single error correcting Galois field multipliers over polynomial basis. The proposed method uses multiple parity prediction circuits to detect and correct logic errors and gives 100% fault coverage both in the functional unit and the parity predi...
 
A Galois Field Based Logic Synthesis Approach with Testability
Found in: VLSI Design, International Conference on
By J. Mathew, H. Rahaman, A.K Singh, A.M. Jabir, D.K Pradhan
Issue Date:January 2008
pp. 629-634
of the most demanding requirements. Efficient testable logic synthesis is one way to tackle the problem. To this end, this paper introduces a new fast efficient graph-based decomposition technique for Boolean functions in finite fields, which utilizes the ...
 
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation
Found in: IEEE Transactions on Computers
By Abusaleh Jabir, Dhiraj Pradhan, T.L. Rajaprabhu, A.K. Singh
Issue Date:August 2007
pp. 1133-1145
This paper presents a technique for representing multiple output binary and word-level functions in GF(N) ($N=p^m$, p a prime number and m a nonzero positive integer) based on decision diagrams (DD). The presented DD is canonical and can be made minimal wi...
 
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields
Found in: IEEE Transactions on Computers
By Abusaleh M. Jabir, Dhiraj K. Pradhan
Issue Date:August 2007
pp. 1119-1132
<p><b>Abstract</b>—This paper presents the generalized theory and an efficient graph-based technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. ...
 
An efficient technique for synthesis and optimization of polynomials in GF(2m)
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew
Issue Date:November 2006
pp. 151-157
This paper presents an efficient technique for synthesis and optimization of polynomials over GF(2m), where m is a non-zero positive integer. The technique is based on a graph-based decomposition and factorization of polynomials over GF(2m), followed by ef...
     
An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m)
Found in: Computer-Aided Design, International Conference on
By A.M. Jabir, D.K. Pradhan, J. Mathew
Issue Date:November 2006
pp. 151-157
This paper presents an efficient technique for synthesis and optimization of polynomials over GF(2<sup>m</sup>), where mis a non-zero positive integer. The technique is based on a graph-based decomposition and factorization of polynomials over ...
 
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By H. Rahaman, J. Mathew, A.M. Jabir, D.K. Pradhan
Issue Date:November 2006
pp. 48-54
A testable implementation of bit parallel multiplier over the finite field GF(2<sup>m</sup>) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2<sup>m</sup>) m...
 
GASIM: a fast Galois field based simulator for functional model
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By D.K. Pradhan, A.K. Singh, T.L. Rajaprabhu, A.M. Jabir
Issue Date:December 2005
pp. 135-142
This paper presents a fast logic simulator based on Galois field. This is designed to act as an underlying tool for all finite field applications considering the fact that simulation plays an important role in all these applications. Three approaches for f...
   
MODD for CF: a representation for fast evaluation of multiple-output functions
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By T.L. Rajaprabhu, A.K. Singh, A.M. Jabir, D.K. Pradhan
Issue Date:November 2004
pp. 61-66
Recently a mathematical framework was presented that bridges the gap between bit level BDD representation and word level representations such as BMD and TED. Here we present an approach that demonstrates that these diagrams admit fast evaluation of circuit...
 
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Abusaleh M. Jabir, Dhiraj K. Pradhan
Issue Date:February 2004
pp. 21388
This paper presents a new decision diagram (DD), called MODD, for multiple output binary and multiple-valued functions. This DD is canonic and can be made minimal with respect to a given variable order. Unlike other reported DDs, our approach can represent...
   
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