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Displaying 1-11 out of 11 total
OpenMDSP: Extending OpenMP to Program Multi-Core DSP
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Jiangzhou He,Wenguang Chen,Guangri Chen,Weimin Zheng,Zhizhong Tang,Handong Ye
Issue Date:October 2011
pp. 288-297
Multi-core Digital Signal Processors (DSP) are widely used in wireless telecommunication, core network transcoding, industrial control, and audio/video processing etc. Comparing with general purpose multi-processors, the multi-core DSPs normally have more ...
A Novel Memory Subsystem Evaluation Framework for Chip Multiprocessors
Found in: High Performance Computing and Communications, 10th IEEE International Conference on
By Fucen Zeng, Lin Qiao, Mingliang Liu, Zhizhong Tang
Issue Date:September 2010
pp. 231-238
This paper presents a fast and cycle-accurate memory subsystem modeling and evaluating framework for Chip Multiprocessors (CMPs), called TSIM (Tsinghua SIMulator), which gives a flexible and extensible approach to evaluating architecture designs, models or...
Understanding the Memory Behavior of Emerging Multi-core Workloads
Found in: Parallel and Distributed Computing, International Symposium on
By Junmin Lin, Yu Chen, Wenlong Li, Aamer Jaleel, Zhizhong Tang
Issue Date:July 2009
pp. 153-160
This paper characterizes the memory behavior on emerging RMS (recognition, mining, and synthesis) workloads for future multi-core processors. As multi-core processors proliferate across different application domains, and the number of on-die cores continue...
Efficient shared cache management through sharing-aware replacement and streaming-aware insertion policy
Found in: Parallel and Distributed Processing Symposium, International
By Yu Chen,Wenlong Li,Changkyu Kim, Zhizhong Tang
Issue Date:May 2009
pp. 1-11
Multi-core processors with shared caches are now commonplace. However, prior works on shared cache management primarily focused on multi-programmed workloads. These schemes consider how to partition the cache space given that simultaneously-running applica...
Performance Characterization of SPEC CPU2006 Benchmarks on Intel and AMD Platform
Found in: Education Technology and Computer Science, International Workshop on
By Shengmei Li, Buqi Cheng, Xingyu Gao, Lin Qiao, Zhizhong Tang
Issue Date:March 2009
pp. 116-121
For understanding the performance differences caused by different computer architectures and optimization technologies, the paper characterizes performance of SPEC CPU2006 benchmarks both on Intel and AMD platform. Using the performance events collected by...
Alphabet Based Selected Character Decoding for Area Efficient Pattern Matching Architecture on FPGAs
Found in: Embedded Software and Systems, Second International Conference on
By Tian Song, Wei Zhang, Zhizhong Tang, Dongsheng Wang
Issue Date:December 2005
pp. 276-283
In this paper, we present an idea of selected character decoding (SCD) based on alphabet for network usage, especially network intrusion detection system(NIDS). SCD extends the approaches using decoder in order to achieve the least number of comparison uni...
Single-Dimension Software Pipelining for Multi-Dimensional Loops
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Hongbo Rong, Zhizhong Tang, R. Govindarajan, Alban Douillet, Guang R. Gao
Issue Date:March 2004
pp. 163
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to outer loops. In this paper, we propose a three-step approach, called Single-dimension Software Pipelining (SSP), to software pipel...
Architecture of the Simplified Chinese Embedded System STARTH
Found in: High-Performance Computing in the Asia-Pacific Region, International Conference on
By Peter Xiangdong Mao, Zhizhong Tang, Michael Chen, Youming Zhang, Vern Zheng
Issue Date:May 2000
pp. 1167
There is a trend for the information products that integrated by computer, communication, and consumer electronics. The OS is required more compact and practical. An embedded system STARTH is developed and based on the core of the Motorola PPSM that is a r...
A New Architecture For Branch-Intensive Loops
Found in: Advances in Parallel and Distributed Computing Conference
By Zhizhong Tang, Chihong Zhang, Sifei Lvand Tao Yu
Issue Date:March 1997
pp. 241
A new VLIW architecture, called GPMB(Global Pipelining of Multi-Branch), is discussed in this paper. The GPMB architecture can handle branch-intensive programs efficiently. With the concept of next address Function, GPMB regards branching as correctly calc...
An Improvement on Data Dependence Analysis Supporting Software Pipelining Technique
Found in: Advances in Parallel and Distributed Computing Conference
By Chihong Zhang, Zhizhong Tang
Issue Date:March 1997
pp. 378
The accuracy of the data dependence analysis of a client program will decide in what an extent the compiler can unleash the power of the potential parallelism of the client program. Most of the current works on dependence analysis are based on the dependen...
Single-dimension software pipelining for multidimensional loops
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Alban Douillet, Guang R. Gao, Hongbo Rong, R. Govindarajan, Zhizhong Tang
Issue Date:March 2007
pp. 7-es
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to outer loops. This paper proposes a three-step approach, called single-dimension software pipelining (SSP), to software pipeline a ...