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Displaying 1-36 out of 36 total
3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers
Found in: 2011 Design, Automation & Test in Europe
By Yi-Chung Chen, Hai Li, Yiran Chen,R E Pino
Issue Date:March 2011
pp. 1-4
Resistive random access memory (ReRAM) has been demonstrated as a promising non-volatile memory technology with features such as high density, low power, good scalability, easy fabrication and compatibility to the existing CMOS technology. The conventional...
   
Utilizing PCM for Energy Optimization in Embedded Systems
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By Zili Shao,Yongpan Liu,Yiran Chen,Tao Li
Issue Date:August 2012
pp. 398-403
Due to its high density, bit alterability, and low standby power, phase change memory (PCM) is considered as a promising DRAM alternative. In embedded systems, especially battery-driven mobile devices, energy is one of the most important performance metric...
 
Quantitative Study of Individual Emotional States in Social Networks
Found in: IEEE Transactions on Affective Computing
By Jie Tang, Yuan Zhang, Jimeng Sun, Jinhai Rao, Wenjing Yu, Yiran Chen,A. C. M. Fong
Issue Date:April 2012
pp. 132-144
Marketing strategies without emotion will not work. Emotion stimulates the mind 3,000 times quicker than rational thought. Such emotion invokes either a positive or a negative response and physical expressions. Understanding the underlying dynamics of user...
 
Architecting a common-source-line array for bipolar non-volatile memory devices
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By Bo Zhao, Jun Yang, Youtao Zhang, Yiran Chen, Hai Li
Issue Date:March 2012
pp. 1451-1454
Traditional array organization of bipolar non-volatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck of density improvement. In this paper we...
 
Spintronic memristor based temperature sensor design with CMOS current reference
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen,R. E. Pino
Issue Date:March 2012
pp. 1301-1306
As the technology scales down, the increased power density brings in significant system reliability issues. Therefore, the temperature monitoring and the induced power management become more and more critical. The thermal fluctuation effects of the recentl...
 
Asymmetry of MTJ switching and its implication to STT-RAM designs
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By Yaojun Zhang, Xiaobin Wang, Yong Li,A. K. Jones, Yiran Chen
Issue Date:March 2012
pp. 1313-1318
As one promising candidate for next-generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, non-volatility, and goo...
 
STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view
Found in: Computer-Aided Design, International Conference on
By Yaojun Zhang,Xiaobin Wang,Yiran Chen
Issue Date:November 2011
pp. 471-477
The rapidly increased demands for memory in electronic industry and the significant technical scaling challenges of all conventional memory technologies motivated the researches on the next generation memory technology. As one promising candidate, spin-tra...
 
MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Ping Zhou,Bo Zhao,Youtao Zhang,Jun Yang,Yiran Chen
Issue Date:October 2011
pp. 207-208
Memristor, a long postulated yet missing circuit element, has recently emerged as a promising device in non-volatile memory technologies. However, beyond its use as memory cell, it is challenging to integrate memristor in modern architectures for general p...
 
MoodCast: Emotion Prediction via Dynamic Continuous Factor Graph Model
Found in: Data Mining, IEEE International Conference on
By Yuan Zhang, Jie Tang, Jimeng Sun, Yiran Chen, Jinghai Rao
Issue Date:December 2010
pp. 1193-1198
Human emotion is one important underlying force affecting and affected by the dynamics of social networks. An interesting question is “can we predict a person’s mood based on his historic emotion log and his social network?”. In this paper, we propose a Mo...
 
Compact modeling and corner analysis of spintronic memristor
Found in: Nanoscale Architectures, IEEE International Symposium on
By Yiran Chen, Xiaobin Wang
Issue Date:July 2009
pp. 7-12
The 4<sup>th</sup> fundamental circuit elements — memristor received significant attentions after a real device was recently demonstrated for the first time. Besides the solid-state thin film memristive device, sprintonic memristor was also inv...
 
Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Hai Li, Haiwen Xi, Yiran Chen, John Stricklin, Xiaobin Wang, Tong Zhang
Issue Date:May 2009
pp. 217-222
Thermal-assisted spin-transfer torque random access memory (STT-RAM) has been considered as a promising candidate of next-generation nonvolatile memory technology. We conducted finite element simulation on thermal dynamics in the programming process of the...
 
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Found in: Low Power Electronics and Design, International Symposium on
By Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
Issue Date:August 2007
pp. 195-200
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, th...
 
Statistical Timing Analysis Considering Spatial Correlations
Found in: Quality Electronic Design, International Symposium on
By Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen
Issue Date:March 2007
pp. 102-107
In this paper, we present an efficient algorithm to predict the probability distribution of the circuit delay while accounting for spatial correlations. We exploit the structure of the covariance matrix to decouple the correlated variables to independent o...
 
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
Found in: Quality Electronic Design, International Symposium on
By Dongku Kang, Yiran Chen, Kaushik Roy
Issue Date:March 2005
pp. 48-53
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for high-level synthesis. By evaluating power supply noise in the early design stage...
 
Priority Assignment Optimization for Minimization of Current Surge in High Performance Power Efficient Clock-gated Microprocessor
Found in: Asia and South Pacific Design Automation Conference
By Yiran Chen, Kaushik Roy, Cheng-Kok Koh
Issue Date:January 2004
pp. 893-898
We propose an integrated architectural/physical-planning approach named priority assignment optimization to minimize the current surge in high performance power efficient clock-gated microprocessors. The proposed approach balances the current demands acros...
 
Deterministic Clock Gating for Microprocessor Power Reduction
Found in: High-Performance Computer Architecture, International Symposium on
By Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
Issue Date:February 2003
pp. 113
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline balancing (PLB), a previous technique, is essentially a methodology to clock-ga...
 
Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache
Found in: IEEE Transactions on Computers
By Qingan Li,Yanxiang He,Li Jianhua,Liang Shi,Yiran Chen,Chun Xue
Issue Date:February 2015
pp. 1
Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features such as high storage density and ultra low leakage power. However, long write latency and high write energy are the two challenges for STTRAM. R...
 
Mobile devices user: the subscriber and also the publisher of real-time OLED display power management plan
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Chun Jason Xue, Mengying Zhao, Xiang Chen, Yiran Chen
Issue Date:November 2012
pp. 687-690
OLED (Organic Light Emitting Diode) technology has already been adopted in many modern smart mobile devices, including cellphones, tablets, laptop etc. However, the power dissipation of displays in some applications like real-time video streaming, signific...
     
Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Beiye Liu, Chun Jason Xue, Mengying Zhao, Xiang Chen, Xiaojun Guo, Yiran Chen
Issue Date:November 2012
pp. 516-522
OLED is becoming the main stream display for mobile devices. The process variations of thin-film transistors (TFT) and the aging degradation of OLED devices severely impact the display quality and the user experience on mobile devices throughout lifetime. ...
     
Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By Hai Li, Xiang Chen, Yaojun Zhang, Yiran Chen, Zhenyu Sun
Issue Date:June 2012
pp. 1-16
In this article, we propose a data storage system with the emerging nonvolatile memory technologies used for the implantable electrocardiography (ECG) recorder. The proposed storage system can record the digitalized real-time ECG waveforms continuously ins...
     
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Liang Shi, Yinlong Xu, Yiran Chen, Chun Jason Xue, Jianhua Li, Qingan Li, Wei Wang
Issue Date:December 2013
pp. 1-23
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement because of its excellent features, such as fast read access, high density, low leakage power, and CMOS technology compatibility. However, wide adoption of STT-RAM as cache mem...
     
C1C: A configurable, compiler-guided STT-RAM L1 cache
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Alex K. Jones, Hai LI, Yaojun Zhang, Yiran Chen, Yong Li
Issue Date:December 2013
pp. 1-22
Spin-Transfer Torque RAM (STT-RAM), a promising alternative to SRAM for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. Recently, STT-RAM has been proposed for L1 caches by relaxi...
     
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Youtao Zhang, Bo Zhao, Hai Li, Jun Yang, Yiran Chen
Issue Date:October 2013
pp. 1-18
Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck for further density improvement. In this ...
     
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By Cheng-Kok Koh, Hai Li, Weng-Fai Wong, Wujie Wen, Yaojun Zhang, Yiran Chen
Issue Date:May 2013
pp. 1-22
It has been predicted that a processor's caches could occupy as much as 90% of chip area a few technology nodes from the current ones. In this article, we investigate the use of multilevel spin-transfer torque RAM (STT-RAM) cells in the design of pr...
     
A thermal and process variation aware MTJ switching model and its applications in soft error analysis
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Peiyuan Wang, Rajiv Joshi, Rouwaida Kanj, Wei Zhang, Yiran Chen
Issue Date:November 2012
pp. 720-727
Spin-transfer torque random access memory (STT-RAM) has recently gained increased attentions from circuit design and architecture societies. Although STT-RAM offers a good combination of small cell size, nanosecond access time and non-volatility for embedd...
     
Multi-level cell STT-RAM: is it realistic or just a dream?
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Guangyu Sun, Lu Zhang, Wujie Wen, Yaojun Zhang, Yiran Chen
Issue Date:November 2012
pp. 526-532
Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT...
     
A software approach for combating asymmetries of non-volatile memories
Found in: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (ISLPED '12)
By Alex K. Jones, Yiran Chen, Yong Li
Issue Date:July 2012
pp. 191-196
The recent advances in non-volatile memory technologies promise the delivery of future high performance and low power computing systems. While these technologies provide attractive features, they exhibit different degrees of asymmetric read/write behavior,...
     
Improving energy efficiency of write-asymmetric memories by log style write
Found in: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (ISLPED '12)
By Guangyu Sun, Yaojun Zhang, Yiran Chen, Yu Wang
Issue Date:July 2012
pp. 173-178
The significant scaling challenges of conventional memories, i.e., SRAM and DRAM, motivated the research on emerging memory technologies. Many promising memory technology candidates, however, suffer from a common issue in their write operations: the switch...
     
Low-power dual-element memristor based memory design
Found in: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED '10)
By Dimin Niu, Yiran Chen, Yuan Xie
Issue Date:August 2010
pp. 25-30
Recently, the emerging memristor device technology has attracted significant research interests due to its distinctive hysteresis characteristic, which potentially can enable novel circuit designs for future VLSI circuits. In particular, characteristics su...
     
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM
Found in: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED '10)
By Hai Li, Tong Zhang, Wei Xu, Wenzhong Zhu, Xiaobin Wang, Yiran Chen
Issue Date:August 2010
pp. 1-6
A nondestructive self-reference read scheme (NSRS) was recently proposed to overcome the bit-to-bit variation in Spin-Transfer Torque Random Access Memory (STT-RAM). In this work, we introduced three magnetic- and circuit-level techniques, including 1) R-I...
     
Impact of process variations on emerging memristor
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Cong Xu, Dimin Niu, Yiran Chen, Yuan Xie
Issue Date:June 2010
pp. 877-882
The memristor, known as the fourth basic two-terminal circuit element, has attracted many research interests since the first real device was developed by HP labs in 2008. The nano-scale memristive device has the potential to construct some novel computing ...
     
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Tong Zhang, Wei Xu, Xiaobin Wang, Yiran Chen
Issue Date:July 2009
pp. 87-90
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic tunneling junction (MTJ) write current threshold variability. In conventional ...
     
Tolerating process variations in large, set-associative caches: The buddy cache
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Cheng-Kok Koh, Hai Li, Weng-Fai Wong, Yiran Chen
Issue Date:June 2009
pp. 1-34
One important trend in today's microprocessor architectures is the increase in size of the processor caches. These caches also tend to be set associative. As technology scales, process variations are expected to increase the fault rates of the SRAM cells t...
     
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Guangyu Sun, Helen Li, Xiangyu Dong, Xiaoxia Wu, Yiran Chen, Yuan Xie
Issue Date:June 2008
pp. 1-30
Magnetic Random Access Memory (MRAM) has been considered as a promising memory technology due to many attractive properties. Integrating MRAM with CMOS logic may incur extra manufacture cost, due to its hybrid magnetic-CMOS fabrication process. Stacking MR...
     
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Found in: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
By Cheng-Kok Koh, Hai Li, Jing Li, Yiran Chen
Issue Date:August 2007
pp. 195-200
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, th...
     
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Cheng-Kok Koh, Hai Li, Kaushik Roy, Yiran Chen
Issue Date:January 2006
pp. 158-163
Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) technique for multi-issue out-of-order pipeline to improve parametric yield with ...
     
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