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Displaying 1-4 out of 4 total
EHSAT Modeling from Algorithm Description for RTL Model Checking
Asian Test Symposium
By Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao
Issue Date:October 2007
This paper presents a new method to translate Verilog HDL into RTL Model combining algorithm description for high level verification. The model could be used in the enhanced version of a state-of-the-art finite-domain satisfiability(SAT) solver EHSAT to ch...
Random stimulus generation with self-tuning
International Conference on Computer Supported Cooperative Work in Design
By Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong
Issue Date:April 2009
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large and complex design in industry. There are two aspects to measure the stimulus g...
Vessel Real-Time Monitoring System Based on AIS Temporal Database
International Conference on Information Management, Innovation Management and Industrial Engineering
By Zheng Pan, Shujun Deng
Issue Date:December 2009
Automatic Identification System (AIS) plays an important role in maritime traffic. AIS is a system that enables ships to exchange information about ships and voyage, such as position, speed, course, and name automatically by VHF radio. This paper proposes ...
EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Jinian Bian, Shujun Deng, Weimin Wu, Xiaoqing Yang, Yanni Zhao
Issue Date:June 2007
This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedur...
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