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Displaying 1-19 out of 19 total
RAW Introduction
Found in: 2012 26th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
By Juergen Becker,Jinian Bian,Christophe Bobda,Rene Cumplido,Michael Huebner
Issue Date:May 2012
pp. 208-212
No summary available.
 
EHSAT Modeling from Algorithm Description for RTL Model Checking
Found in: Asian Test Symposium
By Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao
Issue Date:October 2007
pp. 178-186
This paper presents a new method to translate Verilog HDL into RTL Model combining algorithm description for high level verification. The model could be used in the enhanced version of a state-of-the-art finite-domain satisfiability(SAT) solver EHSAT to ch...
 
Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits
Found in: 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
By Jiliang Zhang,Yaping Lin,Yongqiang Lyu,Ray C.C. Cheung,Wenjie Che,Qiang Zhou,Jinian Bian
Issue Date:April 2013
pp. 227
As reuse-based design methodology has prevailed in FPGA design field, the FPGA core industry is confronted with the increasing threat of cloning attacks. How to protect modular designed hardware IP (HW-IP) cores against non-authorized over-use and redistri...
 
SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator
Found in: 2012 26th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
By Zhongda Yuan,Yuchun Ma,Jinian Bian
Issue Date:May 2012
pp. 443-448
To further exploit the potential of reconfigurable computing, fine-grain, super massive parallel processing SAT solver over reconfigurable hardware accelerator is proposed in this paper as SMPP. By analyzing the traditional SAT solver, we proposed a novel ...
 
Random stimulus generation with self-tuning
Found in: International Conference on Computer Supported Cooperative Work in Design
By Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong
Issue Date:April 2009
pp. 62-65
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large and complex design in industry. There are two aspects to measure the stimulus g...
 
Cell shifting aware of wirelength and overlap
Found in: Quality Electronic Design, International Symposium on
By Liu Dawei, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong
Issue Date:March 2009
pp. 506-510
The technique of cell shifting has the advantage of linearly smoothing the overlap in placement. In the shifting process we should preserve the integrity of the original placement as much as possible and do less damage to the relative locations of the cell...
 
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration
Found in: Quality Electronic Design, International Symposium on
By Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Issue Date:March 2008
pp. 321-324
To enhance the computing ability of the multimedia processor, this paper presents an automated specific instruction customization methodology. Specially, this methodology features a profiling stage which is equipped with a sub-graph matching algorithm. Fur...
 
Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai
Issue Date:March 2007
pp. 279-284
This article proposes an efficient algorithm by module duplication for integration of high-level synthesis and floorplan to optimize the interconnect delay and power. Module duplication can bring down the interconnect wire length among physical modules, th...
 
Extend Force-directed Scheduling for System-level Synthesis in Timeconstrained System-on-Chip Design
Found in: Embedded Software and Systems, Second International Conference on
By Qiang Wu, Renfa Li, Wei Wang, Wei Xie, Jinian Bian, Yunfeng Wang, Haili Wang
Issue Date:December 2005
pp. 174-180
Scheduling time-constrained task graph to minimize resource requirement is a common and important problem in system-level synthesis (SLS) for system-onchip (SoC) designs. Many algorithms have been proposed to address this issue. In this paper, an extended ...
 
PFGASAT— A Genetic SAT Solver Combining Partitioning and Fuzzy Strategies
Found in: Computer Software and Applications Conference, Annual International
By Jianzhou Zhao, Jinian Bian, Weimin Wu
Issue Date:September 2004
pp. 108-113
This paper is concerned with Boolean satisfiability (SAT) Problem. Many researchers are devoted into seeking for new ideas as well as developing more efficient SAT solvers which will improve the development of EDA (Electronic Design Automation). In this pa...
 
Property Classification for Functional Verification Based
Found in: Asian Test Symposium
By Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue
Issue Date:November 2003
pp. 503
<p>Based on the advantages of simulation and model checking with CDFG structure, classified properties are proposed and defined for simulation, CDFG matching, and model checking respectively.</p> <p>With ITC99 benchmarks, the designed pro...
   
FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking
Found in: Asia and South Pacific Design Automation Conference
By Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong
Issue Date:January 1999
pp. 363
In this paper, we defined a new FSM model that based on the synchronous behavior and symbolic representation technique. The algorithm to elaborate the model from the VHDL description of synchronous circuits is presented. By eliminating the unnesessary tran...
 
IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation Algorithm
Found in: Asia and South Pacific Design Automation Conference
By Wangning Long, Yu-Liang Wu, Jinian Bian
Issue Date:January 2000
pp. 415
The well-known ATPG-based alternative wiring technique, RAMBO, has been shown to be very useful because of its proven powerfulness and flexibility in attacking many design automation problems (e.g. logic optimization, circuit partitioning, and post-layout ...
 
ISBA: an independent set-based algorithm for automated partial reconfiguration module generation
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Jinian Bian, Kang Zhao, Ruining He, Yuchun Ma
Issue Date:November 2012
pp. 500-507
Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR de...
     
HyMacs: hybrid memory access optimization based on custom-instruction scheduling
Found in: Proceedings of the 18th ACM Great Lakes symposium on VLSI (GLSVLSI '08)
By Jinian Bian, Kang Zhao, Satoshi Goto, Sheqin Dong, Yang Song
Issue Date:May 2008
pp. 1-37
This paper presents an efficient hybrid memory access optimization system called HyMacs, which integrates the hardware and software optimization strategies in the embedded system design. First, HyMacs features a pre-configuration stage which is equipped wi...
     
EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Jinian Bian, Shujun Deng, Weimin Wu, Xiaoqing Yang, Yanni Zhao
Issue Date:June 2007
pp. 588-593
This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedur...
     
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Found in: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '07)
By Jinian Bian, Ou He, Sheqin Dong, Xianlong Hong, Yuchun Ma
Issue Date:March 2007
pp. 564-569
More and more IP cores are used in modern SOC designing. In order to place IP cores effectively, hierarchical design has been introduced and better supported by fixed-outline floorplanning than outline-free [1]. In this paper, we also consider buffer inser...
     
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Hannah H. Yang, Jinian Bian, Qiang Zhou, Vijay Pitchumani, Xianlong Hong, Zuoyuan Li
Issue Date:April 2006
pp. 325-345
New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged so...
     
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
Found in: Proceedings of the 2000 conference on Asia and South Pacific design automation (ASP-DAC '00)
By Jinian Bian, Wangning Long, Yu-Liang Wu
Issue Date:January 2000
pp. 415-422
Statisticians and data analysts have always used pictorial representations of data (graphs and charts) to discover and explore relationships between variables, and to communicate their results to other people. Developments in computer hardware and software...
     
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