http://www.computer.org/dt IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of Computers is published by the IEEE Computer Society in technical cosponsorship with the IEEE Circuits and Systems Society. en-us Sat, 25 May 2013 10:00:50 GMT http://csdl.computer.org/common/images/logos/dt.gif List of recently published journal articles http://www.computer.org/dt http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2230297 Manufacturing defects in nanoscale tech- nologies have highly complex timing behaviour that is also aected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specied length. The resulting tests can be employed e.g. within the framework of adaptive testing. The methodology is based on encoding the problem as an instance of the Boolean Satisability Problem (SAT) and thereby leverages recent advances in SAT-solving technology. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2230297 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2226201 Considering the increasing complexity of integrated circuit (IC) designs at Nano-Tera scale, multi-core CPUs and many-core GPUs have provided ideal hardware platforms for emerging parallel algorithm developments in electronic design automation (EDA). However, it has become extremely challenging to leverage parallel hardware platforms at extreme scale beyond 22nm and 60GHz where the EDA algorithms, such as circuit simulation, show strong data dependencies. This paper presents data dependency elimination approaches in circuit simulation algorithms such as parasitic extraction, transient simulation and periodic-steady-state (PSS) simulation, which paves the way towards unleashing the underlying power of parallel hardware platforms. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2226201 http://doi.ieeecomputersociety.org/10.1109/MDT.2013.2238578 Open defects in vias are a dominant failure mechanism in nanometer technologies. Their defect probability has increased with the introduction of the copper process, smaller geometries, and via counts on the order of billions for modern integrated circuits. In this work, the aggravated via reliability due to a manufacturing narrowing defect is analyzed.We quantify the reliability risk by estimating the Mean Time to Failure (MTF) as a function of the void size due to narrowing by applying Blacks Law to three possible geometric models for a defective via. Bidirectional current condition in signal paths was considered to estimate electromigration (EM) and self-heating effects. For redundant via structures, the MTF of the good vias was estimated when there is one defective via. Our results show that despite resistive vias showing little disturbance to the signal transmission until severe voiding occurs, the electromigration and self-heating threat are significant even for relatively small initial via voiding. The MTF degradation is significant despite of the bidirectional current condition of signal paths. Hence, our results indicates that new electromigration design rules for signal paths considering the presence of resistive vias are required. http://doi.ieeecomputersociety.org/10.1109/MDT.2013.2238578 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2232964 Soft errors are becoming an important issue for deep submicron technologies. To protect circuits against soft errors, designers routinely introduce modular redundancy to detect and correct these errors. A commonly used technique, Double Modular Redundancy (DMR) involves duplication of the basic module. Conventionally, DMR only allows error detection since voting cannot be used to determine the module in error. Recently, however, it has been found that DMR can, for some circuits, be enhanced to provide soft error correction as well as detection. The general approach, DDMR (Diverse DMR), relies on introducing design diversity between the original and redundant modules so that they produce different error patterns when a soft error occurs. The module in error can be found by examining these patterns. Herein, the generalized approach is described. A number of techniques for producing diverse designs with distinct error patterns are identified and illustrated with examples. New DDMR solutions are presented and finally, the future direction of DDMR research is discussed. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2232964 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2230391 As serial computing performance gains have diminished, there has been a resurgence of interest in parallel computation. For some problems, parallel systems can achieve near linear performance gains; for others, however, the gains are much more modest. In this paper, we focus on factors that limit parallel performance gains, and also highlight a number of myths and misconceptions that have led to errors in the published literature, and vastly inflated performance expectations. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2230391 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2228294 The well-known saying, 'time is money,' is nowhere more true than in the world of electronics. As the pace of this industry continues to increase, seemingly with each new semiconductor process node, the time to market requirements gets shorter and shorter. But at the same time the cost of design has skyrocketed. If you look at the entire design process a few things become clear. First is that the major cost is in the design team itself. Most design teams stay intact for the entire design process. The second is that the cost of design tools is lunch money. One week of design cost will buy all of the tools generally needed for a design team. However these tools need to continually increase the amount of gates they can process and they must continue to increase their speed of execution. That's where parallel processing comes in. The tool that can incorporate these two improvements wins in the EDA marketplace. In order to do this you must develop superior parallel algorithms. That puts parallel computing at the heart of keeping design costs under control. ROI (return on investment) analysis has its place but when you are talking about an inflection point, and parallel computing is an inflection point, ROI analysis misses the point. Today parallel computing is the ticket into the game. Without it you don??t get to play in today's semiconductor design marketplace. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2228294 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2226423 Accurate simulation of analog and mixed-signal circuit designs prior to fabrication is a necessity to confirm that adequate performance is achieved over process, voltage, and environmental variations. With advanced nanometer semiconductor processes, there is the additional challenge of broad noise bandwidths that cause signals and noise to interact. Including the nonlinear interactions of random electronic noise in simulations has therefore become a necessity. Yet, the additional computational burden of including random noise effects in SPICE-accurate circuit simulations has been prohibitive. Discussed here are effective techniques for modifying SPICE algorithms to take full advantage of multicore computing architectures to achieve fast, efficient, and scalable simulations of electronic circuits under the influence of random noise. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2226423 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2226015 At the Electronic System Level (ESL), design validation often relies on discrete event simulation. Recently, Parallel Discrete Event Simulation (PDES) for ESL models has gained attention again as it promises to utilize the existing parallelism in todays multi-core CPU hosts. This paper provides an overview about the advances in parallel simulation approaches. We discuss how synchronous PDES exploits the explicit parallelism in the ESL models and show how an advanced approach, out-of-order PDES, overcomes the limitations of the synchronous approach and breaks the simulation cycle barriers for more efficient utilization of symmetric multiprocessing simulation hosts. To show the benefits of parallel simulation, we present experimental results for three highly parallel benchmarks with nearly linear speedup, and six standard embedded applications with performance improvement around 2x. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2226015 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2223191 Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there is a wide family of iterative multimedia algorithms that cannot be executed with satisfactory performance on Multi-Processor Systems-on-Chip or Graphics Processing Units. For this reason, new methods to design custom hardware circuits that exploit the intrinsic parallelism of multimedia algorithms are needed. As a consequence, in this paper, we propose a novel design method for the definition of hardware systems optimized for a particular class of multimedia iterative algorithms. We have successfully applied the proposed approach to several realworld case studies, such as iterative convolution filters and the Chambolle algorithm, and the proposed design method has been able to automatically implement, for each one of them, a parallel architecture able to meet real-time performance (up to 72 frames per second for the Chambolle algorithm), with on-chip memory requirements from 2 to 3 orders of magnitude smaller than the state-of-the art approaches. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2223191 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2221152 Moving further into the deep-submicron era, the problem of test-induced yield loss due to high power consumption has increasingly worsened. One of the major causes of this problem is shift timing failure, which arises from excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase on a portion of the clock tree. This paper proposes a novel layout-aware scan segmentation design scheme called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation) for avoiding shift timing failures. The proposed scheme searches for an optimal combination of scan segments for simultaneous clocking so as to reduce the switching activity in the proximities of clock trees while maintaining the average power reduction effect of the conventional scan segmentation. Experimental results on benchmark circuits have demonstrated the advantage of the LCTI-SS scheme. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2221152 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2217471 In this paper, we propose an approach to generate high-level test patterns from the arithmetic model of an RTL circuit using a hybrid canonical data structure based on a decision diagram. High-level simplified and fast symbolic path activation strategy as well as input justification is combined with test pattern generation for circuits under consideration. The current approach has been implemented for a range of small to large benchmark circuits. The results clearly demonstrate that tests generated using the proposed method have achieved high fault coverage for known sequential circuit benchmarks in very short CPU time and minimum memory usage. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2217471 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2217111 Testing dynamic specifications, THD (total-harmonic-distortion), SNR(signal-to-noise ratio) and ENOB (effective-number-of-bits), of high-resolution sigma-delta (ÄÓ) converters is extremely challenging due to the requirement of spectrally pure test stimuli with at least 10dB better SNR and THD than converters being tested. In this work, digital pulse sequence at ÄÓ modulator output is made externally observable for test purposes and an optimized test stimulus is generated that maximizes the sensitivity of the modulator output spectrum to device nonlinearities and noise. Two methods for analyzing the observed spectrum are presented: (1) the dynamic specifications are predicted from the digital pulse sequence using prior alternative testing algorithms, and (2) model parameters of the modulator are computed from the modulator output using nonlinear equation-solving algorithms and subsequently used to determine the specifications. The latter allows diagnosis of the causes of failure. Software simulations and hardware experiments are performed to demonstrate the feasibility of the proposed techniques. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2217111 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2215302 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2215302 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2213793 Excessive switching activity during scan operations endangers the reliability of the chip under test. We propose an architectural solution, which we refer to as Expedited-Compact, to mitigate the scan power problem that otherwise creates high heat dissipation and possibly hot spots. Expedited-Compact architecture advances the response compaction operations by utilizing scan chains as buffer. This enables the flushing of the transition-wise costly response data out of the system quickly, providing scan-out power savings. The proposed DfT-based approach is non-intrusive for design flow, requires a very minor investment in area, and in turn delivers significant and predictable savings in test power. The proposed solution reduces average test power without resorting to x-filling, enabling the application of orthogonal x-filling techniques in conjunction. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2213793 http://doi.ieeecomputersociety.org/10.1109/MDT.2012.1 Modern complex ULSI designs require significant investment of engineering resources for successful execution. At the same time, competing requirements for low cost design and faster time to market will constrain the allowable scope of a project. Experienced project managers are often able to intuitively understand the boundaries for successful program execution, but the inability to adequately quantify these relationships makes it difficult to effectively communicate the level of risk inherent in a project plan. Research into how silicon design teams balance design constraints –both at Intel and in other IC design companies – has provided empirical relationships for the limits of organizational dynamics for Integrated Circuit (IC) development. http://doi.ieeecomputersociety.org/10.1109/MDT.2012.1 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.75 The increasing complexity of integrated circuits pushes for more aggressive design optimizations, such as resetting only part of design registers, that can leave some registers in nondeterministic (X) states. Such Xs may invalidate the correctness of logic simulation due to X-optimism and X-pessimism, producing simulation waveforms that can not be trusted. Although formal methods can resolve the nondeterminism problem, they are not scalable enough to handle today's multi-million gate designs. To address this problem, we developed a scalable X-analysis methodology and successfully applied it to solve three real industrial problems --- one identifies missing Xs in RTL designs while the other two remove incorrect Xs to repair gate-level simulation. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.75 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.73 Speed-path debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speed-path debug based on functional patterns can be very expensive. In this paper, we explore speed-path debug techniques based on at-speed scan test patterns. Enhancements are implemented to improve over an earlier proposed scan-based speed-path diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high-performance microprocessor design. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.73 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.72 Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. This enables us to build models faster (since models are now simply wiring diagrams at an appropriate level of abstraction) and to avoid common modeling errors such as inadvertent loss of data due to incorrect timing assumptions. Our models are formal and they are used for model checking as well as dynamic validation and performance modeling. However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning about correctness and for communicating microarchitectural ideas to RTL and circuit designers and validators. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.72 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.70 Evaluation of hardware Intellectual Property (IP) cores is an important step in an IP-based system-on-chip (SoC) design flow. From the perspective of both IP vendors and Integrated Circuit (IC) designers, it is desirable that hardware IPs can be freely evaluated before purchase, similar to their software counterparts. However, protection of these IPs against piracy during evaluation is a major concern for the IP vendors. Existing solutions typically use encryption and vendor-specific toolsets, which may be unacceptable due to lack of flexibility to use in-house or third-party design tools. We propose a novel low-cost solution for hardware IP protection during evaluation, by embedding a hardware Trojan inside an IP in the form of a finite state machine (FSM) with special structure. The Trojan disrupts the normal functional behavior of the IP on occurrence of a sequence of rare events, thereby effectively putting an “expiry date” on the usage of the IP. The Trojan is structurally and functionally obfuscated, thus protecting against potential reverse engineering efforts that target isolation of the Trojan circuit. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.70 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.49 Moore’s law has provided a metronome for semiconductor technology over the past four decades. However, when CMOS transistor feature size and interconnect dimensions approach their fundamental limits, aggressive scaling will no longer play a significant role in performance improvement. How should the semiconductor industry provide new value in each generation of products in such a scenario? While Moore’s law driven scaling has traditionally focused on improving computation performance (through faster clock frequencies and recently, more parallelism) and memory capacity, electronic systems of the future will provide value by being multi-functional. We envision that integrated systems of the future will perform diverse functions (in addition to traditional computation, storage and communication) such as real-time sensing, energy harvesting, and on-chip testing, to name a few. Enabling such diverse functionality with high performance, high reliability and a low energy budget in a single system requires a radical shift in the principles of system design and integration. Instead of focusing on improving the performance of traditional digital CMOS circuits or exploring nanotechnologies for Silicon and CMOS replacements, we espouse cohesive design and integration of multiple device technologies and diverse components in a single heterogeneous system that is high-performance, energy-efficient and reliable. http://doi.ieeecomputersociety.org/10.1109/MDT.2011.49 http://www.computer.org/portal/site/dt/ IEEE Design & Test of Computers http://www.computer.org/portal/site/dt/