Transactions on Computers Media Center

Our volunteers share with the wider community their views and experiences on a variety of topics. The volunteers can range from associate editors to authors, reviewers or members from the research community at large. The interviews are intended to cover a wide spectrum of topics that are relevant to our community. These topics can be in the form of "shared experiences" and "lessons learned" or highlighting a new technological or theoretical breakthrough. We hope that members of the community will actively participate in making this new feature a great success. For information on submitting multimedia content, please click here.

Albert Zomaya

TC EIC

 

A Word from the Editor-in-Chief,
Albert Y. Zomaya

 

 

 

Call for Papers: IEEE Transactions on Computers Special Section on Computer Arithmetic

Guest Editors Alberto Nannarelli, Peter-Michael Seidel, and Ping Tak Peter Tang [http://www.computer.org/portal/web/tc] seeking original manuscripts for the IEEE Transactions on Computers Special Section on Computer Arithmetic. Submission deadline: September 15, 2013.

 

Computer arithmetic is fundamental to the design of general-purpose and domain-specific processors. Novel arithmetic algorithms and hardware designs are needed to satisfy the power-performance requirements of numerically-intensive applications in a variety of areas including scientific computing, cryptography, multimedia, graphics and digital signal processing. Specialized number representations and encodings play a significant role in the design of arithmetic algorithms and their implementations. Additionally, understanding the fundamental properties of finite precision number systems is essential in the engineering of efficient arithmetic algorithms, as well as the current and future emerging technologies are important in influencing the design and the implementation of such algorithms.

The full Call for Papers can be found here: http://www.computer.org/cms/Computer.org/transactions/cfps/cfp_tcsi_arith.pdf

In Their Own Words In Their Own Words
Automated Generation of Performance and Dependability Models for the Assessment of Wireless Sensor Networks

by Catello Di Martino, Marcello Cinque, and Domenico Cotroneo

 

Wireless Sensor Networks (WSNs) are widely recognized as a promising solution to build next-generation monitoring systems. Their industrial uptake is however still compromised by the low level of trust on their performance and dependability. Whereas analytical models represent a valid means to assess non-functional properties via simulation, their wide use is still limited by the complexity and dynamicity of WSNs, which lead to unaffordable modeling costs. To reduce this gap between research achievements and industrial development, we present a framework for the assessment of WSNs based on the automated generation of analytical models. The framework hides modeling details, and it allows designers to focus on simulation results to drive their design choices. Models are generated starting from a high-level specification of the system and by a preliminary characterization of its fault-free behavior, by exploiting behavioral simulators. The benefits of the framework are shown in the context of two case studies, based on the wireless monitoring of civil structures.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.96

A Parallel Hardware Architecture for Real-Time Object Detection with Support Vector Machines

by Christos Kyrkou and Nicosia Theocharis Theocharides

 

Object detection applications are often associated with real-time performance constraints that stem from the embedded environment that they are often deployed in. Consequently, researchers have proposed dedicated hardware architectures, utilizing a variety of classification algorithms targeting object detection. Support Vector Machines (SVMs) is amongst the most popular classification algorithms used in object detection yielding high accuracy rates. However, existing SVM hardware implementations attempting to speedup SVM classification, have either targeted only simple applications, or SVM training. As such, there are limited proposed hardware architectures that are generic enough to be used in a variety of object detection applications. Hence, this work presents a parallel array architecture for SVM-based object detection, in an attempt to show the advantages, and performance benefits that stem from a dedicated hardware solution. The proposed hardware architecture provides parallel processing, resource sharing amongst the processing units, and efficient memory management. Furthermore, the size of the array is scalable to the hardware demands, and can also handle a variety of applications such as multi-class classification problems. A prototype of the proposed architecture was implemented on an FPGA platform and evaluated using three popular detection applications, demonstrating real-time performance (40-122 fps for a variety of applications). 

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.113

PETCAM: A Power Efficient TCAM Architecture for Forwarding Tables

by Tania Banerjee Mishra and Sartaj Sahni

 

Ternary Content Addressable Memory (TCAM) is a hardware device which can support high-speed table lookups and is an attractive solution for applications such as packet forwarding and classification. We investigate various TCAM architectures recently proposed for TCAM power and memory reduction in packet forwarding and show that far better power and memory performance is possible when we use an optimal prefix set for the given routing table. Compared to existing approaches, our experimental results demonstrate that our approach can significantly reduce both power (8% - 98%) and TCAM memory (45% - 78%) requirements.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.84

IEEE Transactions on Computers: Paolo Montuschi

 

After short self introduction, the speaker quickly inform readers and subscribers of the Computer Society Digital Library (CSDL), about the availability in the CSDL of IEEE Transactions on Computer issues for download in an electronic format very suitable for reading on mobile devices. The speaker both presents a couple of visual examples, and provides a web address where additional information on these new features can be found. Finally, the speaker gives a preview on the future collaboration between the on-line Computer Society web-based-only journal Computing Now and the IEEE Transactions on Computers.

For more information on IEEE Transactions on Computers, visit http://www.computer.org/tc

 

IEEE Transactions on Computers: Q&A with Dr. Elisardo Antelo

 

Professor Elisardo Antelo shares his experience as an Associate Editor for the IEEE TC. He also provides us some insights from his research journey.

For more information on IEEE Transactions on Computers, visit http://www.computer.org/tc

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Essential Sets: Industry's Interest in Computer Arithmetic Research: Part I, Dr. Schwarz's view

Dr. Eric Schwarz describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

 

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Essential Sets: Industry's Interest in Computer Arithmetic Research: Part II, Dr. Hu's view

Dr. Hu describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems

Guest editor Cecilia Metra discusses the "Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems" theme issue for IEEE Transactions on Computers. View the issue here:

http://www.computer.org/portal/web/csdl/transactions/tc#3