Transactions on Computers Media Center

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Albert Zomaya

TC EIC

 

A Word from the Editor-in-Chief,
Albert Y. Zomaya

 

 

 

Call for Papers: IEEE Transactions on Computers Special Section on Computer Arithmetic

Guest Editors Alberto Nannarelli, Peter-Michael Seidel, and Ping Tak Peter Tang [http://www.computer.org/portal/web/tc] seeking original manuscripts for the IEEE Transactions on Computers Special Section on Computer Arithmetic. Submission deadline: September 15, 2013.

 

Computer arithmetic is fundamental to the design of general-purpose and domain-specific processors. Novel arithmetic algorithms and hardware designs are needed to satisfy the power-performance requirements of numerically-intensive applications in a variety of areas including scientific computing, cryptography, multimedia, graphics and digital signal processing. Specialized number representations and encodings play a significant role in the design of arithmetic algorithms and their implementations. Additionally, understanding the fundamental properties of finite precision number systems is essential in the engineering of efficient arithmetic algorithms, as well as the current and future emerging technologies are important in influencing the design and the implementation of such algorithms.

The full Call for Papers can be found here: http://www.computer.org/cms/Computer.org/transactions/cfps/cfp_tcsi_arith.pdf

In Their Own Words In Their Own Words
Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning

by Hoang Le and Viktor K. Prasanna

 

Memory efficiency and dynamically updateable data structures for Internet Protocol (IP) lookup have regained much interest in the research community. In this paper, we revisit the classic tree-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially arising in the next-generation IPv6 routing protocol. Due to longer prefix lengths and much larger address space, preprocessing such routing tables for tree-based LPM can significantly increase the number of prefixes and/or memory stages required for IP lookup. We propose a prefix partitioning algorithm (DPP) to divide a given routing table into k groups of disjoint prefixes (k is given). The algorithm employs dynamic programming to determine the optimal split lengths between the groups to minimize the total memory requirement. Our algorithm demonstrates a substantial reduction in the memory footprint compared with those of the state-of-the-art in both IPv4 and IPv6 cases. Two proposed linear pipelined architectures, which achieve high throughput and support incremental updates, are also presented. The proposed algorithm and architectures achieve a memory efficiency of 1 byte of memory for each byte of prefix for both IPv4 and IPv6. As a result, our design scales well to support either larger routing tables, longer prefix lengths, or both. The total memory requirement depends solely on the number of prefixes. Implementations on 45 nm ASIC and a state-of-the-art FPGA device (for a routing table consisting of 330K prefixes) show that our algorithm achieves 980 and 410 million lookups per second, respectively. These results are well suited for 100Gbps lookup. The implementations also scale to support larger routing tables and longer prefix length when we go from IPv4 to IPv6. Additionally, the proposed architectures can easily interface with external SRAMs to ease the limitation of on-chip memory of the target devices.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.130

CPU Accounting for Multicore Processors

by Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, and Mateo Valero

 

In single-threaded processors and Symmetric Multiprocessors the execution time of a task depends on the other tasks it runs with (the workload), since the Operating System (OS) time shares the CPU(s) between tasks in the workload. However, the time accounted to a task is roughly the same regardless of the workload in which the task runs in, since the OS takes into account those periods in which the task is not scheduled onto a CPU. Chip Multiprocessors (CMPs) introduce complexities when accounting CPU utilization, since the CPU time to account to a task not only depends on the time that the task is scheduled onto a CPU, but also on the amount of hardware resources it receives during that period.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.152

Importance of Coherence Protocols with Network Applications on Multi-Core Processors

by Kyueun Yi, Won W. Ro, and Jean-Luc Gaudiot

 

As Internet and information technology have continued developing, the necessity for fast packet processing in computer networks has also grown in importance. All emerging network applications require deep packet classification as well as security-related processing and they should be run at line rates. Hence, network speed and the complexity of network applications will continue increasing and future network processors should simultaneously meet two requirements: high performance and high programmability. We will show that the performance of single processors will not be sufficient to support future demands. Instead, we will have to turn to multi-core processors which can exploit the parallelism in network workloads.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.199

Statistical Reliability Estimation of Microprocessor-based Systems

by A. Savino, A. Benso, A. Bosio, S. Di Carlo, G. Politano, and G. Di Natale

 

What is the probability that the execution state of a given microprocessor running a given application is correct, in a certain working environment with a given soft-error rate? Trying to answer this question using fault injection can be very expensive and time consuming. This paper proposes the baseline for a new methodology, based on microprocessor error probability profiling, that aims at estimating fault injection results without the need of a typical fault injection setup. The proposed methodology is based on two main ideas: a one-time fault-injection analysis of the microprocessor architecture to characterize the probability of successful execution of each of its instructions in presence of a soft-error, and a static and very fast analysis of the control and data flow of the target software application to compute its probability of success. The presented work goes beyond the dependability evaluation problem; it also has the potential to become the backbone for new tools able to help engineers to choose the best hardware and software architecture to structurally maximize the probability of a correct execution of the target software.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.188

Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs

by Naga Durga Prasad Avirneni and Arun Somani

 

The threat of soft error induced system failure in computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two efficient soft error mitigation schemes, namely Soft Error Mitigation (SEM) and Soft and Timing Error Mitigation (STEM), using the approach of multiple clocking of data for protecting combinational logic blocks from soft errors. Our first technique, SEM, based on distributed and temporal voting of three registers, unloads the soft error detection overhead from the critical path of the systems. SEM is also capable of ignoring false errors and recovers from soft errors using in-situ fast recovery avoiding recomputation. Our second technique, STEM, while tolerating soft errors, adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency. We also present a specialized low overhead clock phase management scheme that ably supports our proposed techniques. Timing annotated gate level simulations, using 45nm libraries, of a pipelined adder-multiplier and DLX processor show that both our techniques achieve near 100% fault coverage. For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a conventional triple modular redundancy voter based soft error mitigation scheme, while STEM outperforms SEM by 27.42%.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.31

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Essential Sets: Industry's Interest in Computer Arithmetic Research: Part I, Dr. Schwarz's view

Dr. Eric Schwarz describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

 

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Essential Sets: Industry's Interest in Computer Arithmetic Research: Part II, Dr. Hu's view

Dr. Hu describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems

Guest editor Cecilia Metra discusses the "Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems" theme issue for IEEE Transactions on Computers. View the issue here:

http://www.computer.org/portal/web/csdl/transactions/tc#3