Transactions on Computers Media Center

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Albert Zomaya

TC EIC

 

A Word from the Editor-in-Chief,
Albert Y. Zomaya

 

 

 

Call for Papers: IEEE Transactions on Computers Special Section on Computer Arithmetic

Guest Editors Alberto Nannarelli, Peter-Michael Seidel, and Ping Tak Peter Tang [http://www.computer.org/portal/web/tc] seeking original manuscripts for the IEEE Transactions on Computers Special Section on Computer Arithmetic. Submission deadline: September 15, 2013.

 

Computer arithmetic is fundamental to the design of general-purpose and domain-specific processors. Novel arithmetic algorithms and hardware designs are needed to satisfy the power-performance requirements of numerically-intensive applications in a variety of areas including scientific computing, cryptography, multimedia, graphics and digital signal processing. Specialized number representations and encodings play a significant role in the design of arithmetic algorithms and their implementations. Additionally, understanding the fundamental properties of finite precision number systems is essential in the engineering of efficient arithmetic algorithms, as well as the current and future emerging technologies are important in influencing the design and the implementation of such algorithms.

The full Call for Papers can be found here: http://www.computer.org/cms/Computer.org/transactions/cfps/cfp_tcsi_arith.pdf

In Their Own Words In Their Own Words
An algorithmic and architectural study on Montgomery exponentiation in RNS

by Filippo Gandino, Fabrizio Lamberti, Gianluca Paravati, Jean Claude Bajard, Paolo Montuschi

 

The modular exponentiation on large numbers is a computationally intensive operation. An effective way for performing this operation consists in using Montgomery exponentiation in the Residue Number System (RNS). This paper presents an algorithmic and architectural study of such exponentiation approach. From the algorithmic point of view, the opportunities that come from the reorganization of the operations and the use of precomputation are considered. From the architectural perspective, the design opportunities offered by well-known computer arithmetic techniques are studied, with the aim of developing an efficient arithmetic cell architecture. Furthermore, since the use of efficient RNS bases with a low Hamming weight are being considered with ever more interest (as they are expected to be capable of reducing the overall computational effort, though at the cost of additional constraints on representable numbers), four additional cell architectures specifically tailored to these bases are developed and the trade-off between benefits and drawbacks is carefully explored. Based on the above developments, an overall comparison among all the considered algorithmic approaches and cell architectures is presented, with the aim of providing the reader with an extensive overview of the Montgomery exponentiation opportunities in RNS.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2012.84

Temperature-aware DVFS for Hard Real-time Applications on Multi-core Processors

by Vinay Hanumaiah and Sarma Vrudhula

 

This paper addresses the problem of determining the feasible speeds and voltages of multi-core processors with hard real-time and temperature constraints. This is an important problem, which has applications in time-critical execution of programs like audio and video encoding on application-specific embedded processors. Two problems are solved. The first is the computation of the optimal time-varying voltages and speeds of each core in a heterogeneous multi-core processor, that minimize the makespan–the latest completion time of all tasks, while satisfying timing and temperature constraints. The solution to the makespan minimization problem is then extended to the problem of determining the feasible speeds and voltages that satisfy task deadlines. The methods presented in this paper also provide a theoretical basis and analytical relations between speed, voltage, power and temperature, which provide greater insight into the early-phase design of processors and are also useful for online dynamic thermal management.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.156

Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications

by Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, and Luca Benini

 

Multimedia streaming applications running on next-generation parallel multiprocessor arrays in sub-45nm technology face new challenges related to device and process variability, leading to performance and power variations across the cores. In this context, Quality of Service (QoS), as well as energy efficiency, could be severely impacted by variability. In this work we propose a run-time variability-aware workload distribution technique for enhancing real-time predictability and energy efficiency based on an innovative Linear-Programming + Bin-Packing formulation which can be solved in linear time. We demonstrate our approach on the virtual prototype of a next-generation industrial multi-core platform running representative multimedia applications. Experimental results confirm that our technique compensates variability, while improving energy-efficiency and minimizing deadline violations in presence of performance and power variations across the cores. The proposed policy can save up to 33% of energy with respect to the state-of-the-art policies and 65% of energy with respect to one variability-un-aware task allocation policy while providing better QoS.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.127

Minimizing Energy Consumption of Embedded Systems via Optimal Code Layout

by Chen-Wei Huang and Shiao-Li Tsao

 

As the gap between CPU and memory is widening every year, it is getting harder for CPU to obtain a timely response from main memory. At the same time, accessing energy for registers in CPU to that of SDRAM differs by orders of magnitudes. So a badly designed memory system will drag down the system performance, and also restrain the battery life for portable devices. This situation will be more challenging in the multi-core era, where memory systems have to supply more data at a faster pace and in more energy-efficient manner.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.122

Progressive Congestion Management Based on Packet Marking and Validation Techniques

by Joan-LLuis Ferrer, Elvira Baydal, Antonio Robles, Pedro Lopez, and Jose Duato

 

Congestion management in multistage interconnection networks is a serious problem not completely solved. In order to avoid the degradation of network performance when congestion appears, several congestion management mechanisms have been proposed. Most of these mechanisms are based on explicit congestion notification. For this purpose, switches detect congestion and depending on the applied strategy, packets are marked to warn the source hosts. In response, source hosts apply some corrective actions to adjust their packet injection rate. Although these proposals seem quite effective, they either exhibit some drawbacks or are partial solutions. Some of them introduce some penalties over the flows not responsible for congestion, whereas others can cope only with congestion situations that last for a short time. In this paper, we present an overview of the different strategies to detect and correct congestion in multistage interconnection networks, and propose a new mechanism referred to as Marking and Validation Congestion Management (MVCM), targeted to this kind of lossless networks, and based on a more refined packet marking strategy combined with a fair set of corrective actions, that makes the mechanism able to effectively manage congestion regardless of the congestion degree. Evaluation results show the effectiveness and robustness of the proposed mechanism.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.146

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Essential Sets: Industry's Interest in Computer Arithmetic Research: Part I, Dr. Schwarz's view

Dr. Eric Schwarz describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

 

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Essential Sets: Industry's Interest in Computer Arithmetic Research: Part II, Dr. Hu's view

Dr. Hu describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems

Guest editor Cecilia Metra discusses the "Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems" theme issue for IEEE Transactions on Computers. View the issue here:

http://www.computer.org/portal/web/csdl/transactions/tc#3