Transactions on Computers Media Center

Our volunteers share with the wider community their views and experiences on a variety of topics. The volunteers can range from associate editors to authors, reviewers or members from the research community at large. The interviews are intended to cover a wide spectrum of topics that are relevant to our community. These topics can be in the form of "shared experiences" and "lessons learned" or highlighting a new technological or theoretical breakthrough. We hope that members of the community will actively participate in making this new feature a great success. For information on submitting multimedia content, please click here.

Albert Zomaya

TC EIC

 

A Word from the Editor-in-Chief,
Albert Y. Zomaya

 

 

 

Call for Papers: IEEE Transactions on Computers Special Section on Computer Arithmetic

Guest Editors Alberto Nannarelli, Peter-Michael Seidel, and Ping Tak Peter Tang [http://www.computer.org/portal/web/tc] seeking original manuscripts for the IEEE Transactions on Computers Special Section on Computer Arithmetic. Submission deadline: September 15, 2013.

 

Computer arithmetic is fundamental to the design of general-purpose and domain-specific processors. Novel arithmetic algorithms and hardware designs are needed to satisfy the power-performance requirements of numerically-intensive applications in a variety of areas including scientific computing, cryptography, multimedia, graphics and digital signal processing. Specialized number representations and encodings play a significant role in the design of arithmetic algorithms and their implementations. Additionally, understanding the fundamental properties of finite precision number systems is essential in the engineering of efficient arithmetic algorithms, as well as the current and future emerging technologies are important in influencing the design and the implementation of such algorithms.

The full Call for Papers can be found here: http://www.computer.org/cms/Computer.org/transactions/cfps/cfp_tcsi_arith.pdf

In Their Own Words In Their Own Words
VSPN: VANET-based Secure and Privacy-preserving Navigation

by T.W. Chim, S.M. Yiu, Lucas C.K. Hui and Victor O.K. Li

 

In this paper, we propose a navigation scheme that utilizes the online road information collected by a vehicular ad hoc network (VANET) to guide the drivers to desired destinations in a real-time and distributed manner. The proposed scheme has the advantage of using real-time road conditions to compute a better route and at the same time, the information source can be properly authenticated. To protect the privacy of the drivers, the query (destination) and the driver who issues the query are guaranteed to be unlinkable to any party including the trusted authority. We make use of the idea of anonymous credential to achieve this goal. In addition to authentication and privacy-preserving, our scheme fulfills all other necessary security requirements. Using the real maps of New York and California, we conducted a simulation study on our scheme showing that it is effective in terms of processing delay and providing routes of much shorter travelling time.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2012.188

QCA Systolic Array Design

by Liang Lu, Weiqiang Liu, Maire O’Neill, Earl E. Swartzlander Jr.

 

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in semi-conductor QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology. This research work will lead the way for the design of more complex QCA circuits allowing researchers to develop new QCA design methodologies and demonstrate the full potential of QCA nanotechnology.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2011.234

Analysis of Error Masking and Restoring Properties of Sequential Circuits

by Jinghang Liang, Jie Han, and Fabrizio Lombardi

 

Scaling of CMOS technology into nanometric feature sizes has raised concerns for the reliable operation of logic circuits such as in the presence of soft errors. This paper deals with the analysis of the operation of sequential circuits. As the feedback signals in a sequential circuit can be logically masked by specific combinations of primary inputs, the cumulative effects of soft errors can be eliminated. This phenomenon, referred to as error masking, is related to the presence of so-called restoring inputs and/or the consecutive presence of specific inputs in multiple clock cycles (equivalent to a synchronizing sequence in switching theory). In this paper, error masking is extensively analyzed using the operations of state transition matrices (STMs) and binary decision diagrams (BDDs) of a finite state machine (FSM) model. The characteristics of the state transitions with respect to the correlation between the restoring inputs and the time sequence are mathematically established using STMs; although the applicability of the STM analysis is restricted due to its complexity, the BDD approach is more efficient and scalable for use in the analysis of large circuits. These results are supported by simulations of benchmark circuits and may provide a basis for further devising efficient and robust implementation when designing FSMs.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2012.147

Overview of the SpiNNaker system architecture

by Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown

 

Steve Furber introduces a paper, recently published in IEEE Transactions on Computers, that presents an overview of the architecture of the SpiNNaker massively-parallel neurocomputer. SpiNNaker was designed for brain-modelling applications, and will ultimately employ a million ARM processor cores to model up to a billion spiking neurons in biological real time.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2012.142

Content Discovery and Caching in Mobile Networks with Infrastructure

by F. Malandrino, C. Casetti, C.F. Chiasserini

 

We address content discovery in wireless networks with infrastructure, where mobile nodes store, advertise, and consume content while Broker entities running on infrastructure devices let demand and offer meet. We refer to this paradigm as match-making, highlighting its features within the confines of the standard publish-and-subscribe paradigm. We study its performance in terms of success probability of a content query, a parameter that we strive to increase by acting as follows: 1) We design a credit-based scheme that makes it convenient for rational users to provide their content (thus discouraging free-riding behavior), and it guarantees them a fair treatment. 2) We increase the availability of either popular or rare content, through an efficient caching scheme. 3) We counter malicious nodes whose objective is to disrupt the system performance by not providing the content they advertise. To counter the latter as well as free riders, we introduce a feedback mechanism that enables a Broker to tell apart well- and misbehaving nodes in a very reliable manner, and to ban the latter. The properties of our match-making scheme are analyzed through game theory. Furthermore, via ns-3 simulations, we show its resilience to different attacks by malicious users and its good performance with respect to other existing solutions.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2011.216

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Essential Sets: Industry's Interest in Computer Arithmetic Research: Part I, Dr. Schwarz's view

Dr. Eric Schwarz describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

 

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Essential Sets: Industry's Interest in Computer Arithmetic Research: Part II, Dr. Hu's view

Dr. Hu describes the important aspects of computer arithmetic research. He provides a list of current questions that need to be solved by research and also what topics are the most interesting to industry.

Purchase the Essential Sets here:

Volume 1:

www.computer.org/portal/web/store?product_id=ES0000033&category_id=TechSets

Volume 2:

www.computer.org/portal/web/store?product_id=ES0000034&category_id=TechSets

 

Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems

Guest editor Cecilia Metra discusses the "Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems" theme issue for IEEE Transactions on Computers. View the issue here:

http://www.computer.org/portal/web/csdl/transactions/tc#3