Transactions on Computers

VSPN: VANET-based Secure and Privacy-preserving Navigation

2013-03-21T16:16:15Z

by T.W. Chim, S.M. Yiu, Lucas C.K. Hui and Victor O.K. Li

In this paper, we propose a navigation scheme that utilizes the online road information collected by a vehicular ad hoc network (VANET) to guide the drivers to desired destinations in a real-time and distributed manner. The proposed scheme has the advantage of using real-time road conditions to compute a better route and at the same time, the information source can be properly authenticated. To protect the privacy of the drivers, the query (destination) and the driver who issues the query are guaranteed to be unlinkable to any party including the trusted authority. We make use of the idea of anonymous credential to achieve this goal. In addition to authentication and privacy-preserving, our scheme fulfills all other necessary security requirements. Using the real maps of New York and California, we conducted a simulation study on our scheme showing that it is effective in terms of processing delay and providing routes of much shorter travelling time.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2012.188

QCA Systolic Array Design

2013-03-13T21:54:25Z

by Liang Lu, Weiqiang Liu, Maire O’Neill, Earl E. Swartzlander Jr.

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in semi-conductor QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology. This research work will lead the way for the design of more complex QCA circuits allowing researchers to develop new QCA design methodologies and demonstrate the full potential of QCA nanotechnology.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2011.234

Analysis of Error Masking and Restoring Properties of Sequential Circuits

2013-02-14T23:53:42Z

by Jinghang Liang, Jie Han, and Fabrizio Lombardi

Scaling of CMOS technology into nanometric feature sizes has raised concerns for the reliable operation of logic circuits such as in the presence of soft errors. This paper deals with the analysis of the operation of sequential circuits. As the feedback signals in a sequential circuit can be logically masked by specific combinations of primary inputs, the cumulative effects of soft errors can be eliminated. This phenomenon, referred to as error masking, is related to the presence of so-called restoring inputs and/or the consecutive presence of specific inputs in multiple clock cycles (equivalent to a synchronizing sequence in switching theory). In this paper, error masking is extensively analyzed using the operations of state transition matrices (STMs) and binary decision diagrams (BDDs) of a finite state machine (FSM) model. The characteristics of the state transitions with respect to the correlation between the restoring inputs and the time sequence are mathematically established using STMs; although the applicability of the STM analysis is restricted due to its complexity, the BDD approach is more efficient and scalable for use in the analysis of large circuits. These results are supported by simulations of benchmark circuits and may provide a basis for further devising efficient and robust implementation when designing FSMs.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2012.147

Overview of the SpiNNaker system architecture

2013-02-05T23:46:22Z

by Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown

Steve Furber introduces a paper, recently published in IEEE Transactions on Computers, that presents an overview of the architecture of the SpiNNaker massively-parallel neurocomputer. SpiNNaker was designed for brain-modelling applications, and will ultimately employ a million ARM processor cores to model up to a billion spiking neurons in biological real time.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2012.142

Content Discovery and Caching in Mobile Networks with Infrastructure

2013-01-15T17:15:31Z

by F. Malandrino, C. Casetti, C.F. Chiasserini

We address content discovery in wireless networks with infrastructure, where mobile nodes store, advertise, and consume content while Broker entities running on infrastructure devices let demand and offer meet. We refer to this paradigm as match-making, highlighting its features within the confines of the standard publish-and-subscribe paradigm. We study its performance in terms of success probability of a content query, a parameter that we strive to increase by acting as follows: 1) We design a credit-based scheme that makes it convenient for rational users to provide their content (thus discouraging free-riding behavior), and it guarantees them a fair treatment. 2) We increase the availability of either popular or rare content, through an efficient caching scheme. 3) We counter malicious nodes whose objective is to disrupt the system performance by not providing the content they advertise. To counter the latter as well as free riders, we introduce a feedback mechanism that enables a Broker to tell apart well- and misbehaving nodes in a very reliable manner, and to ban the latter. The properties of our match-making scheme are analyzed through game theory. Furthermore, via ns-3 simulations, we show its resilience to different attacks by malicious users and its good performance with respect to other existing solutions.

The full article can be found here:

http://doi.ieeecomputersociety.org/10.1109/TC.2011.216

An algorithmic and architectural study on Montgomery exponentiation in RNS

2012-10-17T16:09:30Z

by Filippo Gandino, Fabrizio Lamberti, Gianluca Paravati, Jean Claude Bajard, Paolo Montuschi

The modular exponentiation on large numbers is a computationally intensive operation. An effective way for performing this operation consists in using Montgomery exponentiation in the Residue Number System (RNS). This paper presents an algorithmic and architectural study of such exponentiation approach. From the algorithmic point of view, the opportunities that come from the reorganization of the operations and the use of precomputation are considered. From the architectural perspective, the design opportunities offered by well-known computer arithmetic techniques are studied, with the aim of developing an efficient arithmetic cell architecture. Furthermore, since the use of efficient RNS bases with a low Hamming weight are being considered with ever more interest (as they are expected to be capable of reducing the overall computational effort, though at the cost of additional constraints on representable numbers), four additional cell architectures specifically tailored to these bases are developed and the trade-off between benefits and drawbacks is carefully explored. Based on the above developments, an overall comparison among all the considered algorithmic approaches and cell architectures is presented, with the aim of providing the reader with an extensive overview of the Montgomery exponentiation opportunities in RNS.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2012.84

Temperature-aware DVFS for Hard Real-time Applications on Multi-core Processors

2012-08-08T23:25:25Z

by Vinay Hanumaiah and Sarma Vrudhula

This paper addresses the problem of determining the feasible speeds and voltages of multi-core processors with hard real-time and temperature constraints. This is an important problem, which has applications in time-critical execution of programs like audio and video encoding on application-specific embedded processors. Two problems are solved. The first is the computation of the optimal time-varying voltages and speeds of each core in a heterogeneous multi-core processor, that minimize the makespan–the latest completion time of all tasks, while satisfying timing and temperature constraints. The solution to the makespan minimization problem is then extended to the problem of determining the feasible speeds and voltages that satisfy task deadlines. The methods presented in this paper also provide a theoretical basis and analytical relations between speed, voltage, power and temperature, which provide greater insight into the early-phase design of processors and are also useful for online dynamic thermal management.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.156

Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications

2012-08-08T23:17:07Z

by Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, and Luca Benini

Multimedia streaming applications running on next-generation parallel multiprocessor arrays in sub-45nm technology face new challenges related to device and process variability, leading to performance and power variations across the cores. In this context, Quality of Service (QoS), as well as energy efficiency, could be severely impacted by variability. In this work we propose a run-time variability-aware workload distribution technique for enhancing real-time predictability and energy efficiency based on an innovative Linear-Programming + Bin-Packing formulation which can be solved in linear time. We demonstrate our approach on the virtual prototype of a next-generation industrial multi-core platform running representative multimedia applications. Experimental results confirm that our technique compensates variability, while improving energy-efficiency and minimizing deadline violations in presence of performance and power variations across the cores. The proposed policy can save up to 33% of energy with respect to the state-of-the-art policies and 65% of energy with respect to one variability-un-aware task allocation policy while providing better QoS.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.127

Minimizing Energy Consumption of Embedded Systems via Optimal Code Layout

2012-05-25T18:00:13Z

by Chen-Wei Huang and Shiao-Li Tsao

As the gap between CPU and memory is widening every year, it is getting harder for CPU to obtain a timely response from main memory. At the same time, accessing energy for registers in CPU to that of SDRAM differs by orders of magnitudes. So a badly designed memory system will drag down the system performance, and also restrain the battery life for portable devices. This situation will be more challenging in the multi-core era, where memory systems have to supply more data at a faster pace and in more energy-efficient manner.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.122

Progressive Congestion Management Based on Packet Marking and Validation Techniques

2012-05-25T17:33:22Z

by Joan-LLuis Ferrer, Elvira Baydal, Antonio Robles, Pedro Lopez, and Jose Duato

Congestion management in multistage interconnection networks is a serious problem not completely solved. In order to avoid the degradation of network performance when congestion appears, several congestion management mechanisms have been proposed. Most of these mechanisms are based on explicit congestion notification. For this purpose, switches detect congestion and depending on the applied strategy, packets are marked to warn the source hosts. In response, source hosts apply some corrective actions to adjust their packet injection rate. Although these proposals seem quite effective, they either exhibit some drawbacks or are partial solutions. Some of them introduce some penalties over the flows not responsible for congestion, whereas others can cope only with congestion situations that last for a short time. In this paper, we present an overview of the different strategies to detect and correct congestion in multistage interconnection networks, and propose a new mechanism referred to as Marking and Validation Congestion Management (MVCM), targeted to this kind of lossless networks, and based on a more refined packet marking strategy combined with a fair set of corrective actions, that makes the mechanism able to effectively manage congestion regardless of the congestion degree. Evaluation results show the effectiveness and robustness of the proposed mechanism.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.146

Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning

2012-05-25T00:14:12Z

by Hoang Le and Viktor K. Prasanna

Memory efficiency and dynamically updateable data structures for Internet Protocol (IP) lookup have regained much interest in the research community. In this paper, we revisit the classic tree-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially arising in the next-generation IPv6 routing protocol. Due to longer prefix lengths and much larger address space, preprocessing such routing tables for tree-based LPM can significantly increase the number of prefixes and/or memory stages required for IP lookup. We propose a prefix partitioning algorithm (DPP) to divide a given routing table into k groups of disjoint prefixes (k is given). The algorithm employs dynamic programming to determine the optimal split lengths between the groups to minimize the total memory requirement. Our algorithm demonstrates a substantial reduction in the memory footprint compared with those of the state-of-the-art in both IPv4 and IPv6 cases. Two proposed linear pipelined architectures, which achieve high throughput and support incremental updates, are also presented. The proposed algorithm and architectures achieve a memory efficiency of 1 byte of memory for each byte of prefix for both IPv4 and IPv6. As a result, our design scales well to support either larger routing tables, longer prefix lengths, or both. The total memory requirement depends solely on the number of prefixes. Implementations on 45 nm ASIC and a state-of-the-art FPGA device (for a routing table consisting of 330K prefixes) show that our algorithm achieves 980 and 410 million lookups per second, respectively. These results are well suited for 100Gbps lookup. The implementations also scale to support larger routing tables and longer prefix length when we go from IPv4 to IPv6. Additionally, the proposed architectures can easily interface with external SRAMs to ease the limitation of on-chip memory of the target devices.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.130

CPU Accounting for Multicore Processors

2012-03-13T19:12:19Z

by Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, and Mateo Valero

In single-threaded processors and Symmetric Multiprocessors the execution time of a task depends on the other tasks it runs with (the workload), since the Operating System (OS) time shares the CPU(s) between tasks in the workload. However, the time accounted to a task is roughly the same regardless of the workload in which the task runs in, since the OS takes into account those periods in which the task is not scheduled onto a CPU. Chip Multiprocessors (CMPs) introduce complexities when accounting CPU utilization, since the CPU time to account to a task not only depends on the time that the task is scheduled onto a CPU, but also on the amount of hardware resources it receives during that period.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.152

Importance of Coherence Protocols with Network Applications on Multi-Core Processors

2012-03-13T19:00:18Z

by Kyueun Yi, Won W. Ro, and Jean-Luc Gaudiot

As Internet and information technology have continued developing, the necessity for fast packet processing in computer networks has also grown in importance. All emerging network applications require deep packet classification as well as security-related processing and they should be run at line rates. Hence, network speed and the complexity of network applications will continue increasing and future network processors should simultaneously meet two requirements: high performance and high programmability. We will show that the performance of single processors will not be sufficient to support future demands. Instead, we will have to turn to multi-core processors which can exploit the parallelism in network workloads.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.199

Statistical Reliability Estimation of Microprocessor-based Systems

2012-01-24T00:19:00Z

by A. Savino, A. Benso, A. Bosio, S. Di Carlo, G. Politano, and G. Di Natale

What is the probability that the execution state of a given microprocessor running a given application is correct, in a certain working environment with a given soft-error rate? Trying to answer this question using fault injection can be very expensive and time consuming. This paper proposes the baseline for a new methodology, based on microprocessor error probability profiling, that aims at estimating fault injection results without the need of a typical fault injection setup. The proposed methodology is based on two main ideas: a one-time fault-injection analysis of the microprocessor architecture to characterize the probability of successful execution of each of its instructions in presence of a soft-error, and a static and very fast analysis of the control and data flow of the target software application to compute its probability of success. The presented work goes beyond the dependability evaluation problem; it also has the potential to become the backbone for new tools able to help engineers to choose the best hardware and software architecture to structurally maximize the probability of a correct execution of the target software.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.188

Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs

2012-01-24T00:20:10Z

by Naga Durga Prasad Avirneni and Arun Somani

The threat of soft error induced system failure in computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two efficient soft error mitigation schemes, namely Soft Error Mitigation (SEM) and Soft and Timing Error Mitigation (STEM), using the approach of multiple clocking of data for protecting combinational logic blocks from soft errors. Our first technique, SEM, based on distributed and temporal voting of three registers, unloads the soft error detection overhead from the critical path of the systems. SEM is also capable of ignoring false errors and recovers from soft errors using in-situ fast recovery avoiding recomputation. Our second technique, STEM, while tolerating soft errors, adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency. We also present a specialized low overhead clock phase management scheme that ably supports our proposed techniques. Timing annotated gate level simulations, using 45nm libraries, of a pipelined adder-multiplier and DLX processor show that both our techniques achieve near 100% fault coverage. For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a conventional triple modular redundancy voter based soft error mitigation scheme, while STEM outperforms SEM by 27.42%.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.31

Automated Generation of Performance and Dependability Models for the Assessment of Wireless Sensor Networks

2011-12-01T19:29:52Z

by Catello Di Martino, Marcello Cinque, and Domenico Cotroneo

Wireless Sensor Networks (WSNs) are widely recognized as a promising solution to build next-generation monitoring systems. Their industrial uptake is however still compromised by the low level of trust on their performance and dependability. Whereas analytical models represent a valid means to assess non-functional properties via simulation, their wide use is still limited by the complexity and dynamicity of WSNs, which lead to unaffordable modeling costs. To reduce this gap between research achievements and industrial development, we present a framework for the assessment of WSNs based on the automated generation of analytical models. The framework hides modeling details, and it allows designers to focus on simulation results to drive their design choices. Models are generated starting from a high-level specification of the system and by a preliminary characterization of its fault-free behavior, by exploiting behavioral simulators. The benefits of the framework are shown in the context of two case studies, based on the wireless monitoring of civil structures.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.96

A Parallel Hardware Architecture for Real-Time Object Detection with Support Vector Machines

2012-01-24T00:20:48Z

by Christos Kyrkou and Nicosia Theocharis Theocharides

Object detection applications are often associated with real-time performance constraints that stem from the embedded environment that they are often deployed in. Consequently, researchers have proposed dedicated hardware architectures, utilizing a variety of classification algorithms targeting object detection. Support Vector Machines (SVMs) is amongst the most popular classification algorithms used in object detection yielding high accuracy rates. However, existing SVM hardware implementations attempting to speedup SVM classification, have either targeted only simple applications, or SVM training. As such, there are limited proposed hardware architectures that are generic enough to be used in a variety of object detection applications. Hence, this work presents a parallel array architecture for SVM-based object detection, in an attempt to show the advantages, and performance benefits that stem from a dedicated hardware solution. The proposed hardware architecture provides parallel processing, resource sharing amongst the processing units, and efficient memory management. Furthermore, the size of the array is scalable to the hardware demands, and can also handle a variety of applications such as multi-class classification problems. A prototype of the proposed architecture was implemented on an FPGA platform and evaluated using three popular detection applications, demonstrating real-time performance (40-122 fps for a variety of applications).

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.113

PETCAM: A Power Efficient TCAM Architecture for Forwarding Tables

2011-12-01T19:28:06Z

by Tania Banerjee Mishra and Sartaj Sahni

Ternary Content Addressable Memory (TCAM) is a hardware device which can support high-speed table lookups and is an attractive solution for applications such as packet forwarding and classification. We investigate various TCAM architectures recently proposed for TCAM power and memory reduction in packet forwarding and show that far better power and memory performance is possible when we use an optimal prefix set for the given routing table. Compared to existing approaches, our experimental results demonstrate that our approach can significantly reduce both power (8% - 98%) and TCAM memory (45% - 78%) requirements.

The full article can be found here: http://doi.ieeecomputersociety.org/10.1109/TC.2011.84

IEEE Transactions on Computers: Paolo Montuschi

2011-10-07T16:19:48Z

After short self introduction, the speaker quickly inform readers and subscribers of the Computer Society Digital Library (CSDL), about the availability in the CSDL of IEEE Transactions on Computer issues for download in an electronic format very suitable for reading on mobile devices. The speaker both presents a couple of visual examples, and provides a web address where additional information on these new features can be found. Finally, the speaker gives a preview on the future collaboration between the on-line Computer Society web-based-only journal Computing Now and the IEEE Transactions on Computers.

For more information on IEEE Transactions on Computers, visit http://www.computer.org/tc

IEEE Transactions on Computers: Q&A with Dr. Elisardo Antelo

2011-10-07T16:18:06Z

Professor Elisardo Antelo shares his experience as an Associate Editor for the IEEE TC. He also provides us some insights from his research journey.

For more information on IEEE Transactions on Computers, visit http://www.computer.org/tc