TCuARCH Chair Candidate

Sotirios Ziavras

BIOSKETCH:

Dr. Sotirios Ziavras is Full Professor in the Electrical and Computer Engineering (ECE) Department at the New Jersey Institute of Technology (NJIT), the Director of the CAPPL (Computer Architecture and Parallel Processing) Laboratory, and Senior Administrator in NJIT's Graduate Studies Office (AY2012-2013).

He received the Diploma in Electrical Engineering from the National Technical University of Athens, Greece (1984) and the D.Sc. in Computer Science from George Washington University (1990). He was with the Center for Automation Research at the University of Maryland, College Park from 1988 to 1989, focusing on supercomputing techniques for computer vision and numerical analysis. He was a visiting Professor of ECE at George Mason University in Spring 1990. He joined NJIT in Fall 1990 as an Assistant Professor. He has served as the Associate Chair for Graduate Studies in ECE for four years.  He also received in 1996 a joint appointment in the Computer Science Department.

He received in 2011 NJIT's award in the category "Excellence in Graduate Instruction." He has advised 11 Ph.D. students, 7 Postdocs, 30 M.S. Thesis students, and dozens of other students for M.S. Project and Senior Project work. He is currently advising 4 Ph.D. students. He has served in many leadership roles at NJIT and in the professional community (e.g., General Chair or Program Chair of IEEE-sponsored conferences, Journal Editor, organizer of special sessions on conferences, etc.).

He has received an excess of $2,000,000 in grants from the National Science Foundation, U.S. Department of Energy, AT&T, etc. He has published about 170 research papers. His main research interests are chip multiprocessors, shared accelerator design for multicore processors, embedded computing systems, reconfigurable computing, power-aware designs, hardware prototyping using FPGAs, and parallel and distributed processing).

POSITION STATEMENT:

The field of Microprogramming and Microarchitecture is ripe for more conferences and journals. Some of them may be created based on cooperative efforts with other organizations, such as HiPEAC. 

Because of the huge number of silicon resources in multicore processor chips that, however, are restricted from achieving their full potential due to prohibitively low off-chip I/O bandwidths, the design of future data-hungry multicore and manycore processors presents us with a set of interesting problems. Even though some of these problems have been investigated before without receiving very noticeable attention by the research community, they should be expected to get a renewed life. Some of these problems are: 

•             Single-core processors consisting of distributed CPU resources on the multicore processor chip. Distributed CPUs will be needed to deal effectively with power dissipation problems while maintaining high performance.

•             Asynchronous CPUs that have the potential to become common due to the application of DVFS approaches by intelligent runtime power and performance management processes.

•             Heterogeneous multicore processors that contain various types of conventional processors with diverse power and performance characteristics.

•             Heterogeneous mulicore processors that also contain specialized hardware accelerators (e.g., scalable vector and GPU units, cryptographic units).

•             Heterogeneous multicore processors that also contain reconfigurable regions for static-time or dynamic-time configuration. Multicore chips already exist that contain embedded cores implemented with fixed logic as well as reconfigurable regions implemented with FPGA logic (e.g., Xilinx Zynq-7000 SoC that contains two hardwired ARM cores).

•             Multicore processors that can afford some errors for certain applications. As a result, approximate results may be acceptable after faults, compared to accurate results that may require very expensive operations (e.g., a large number of off-chip accesses to fetch again data to rerun parts of the application).

•             Microprogramming may present us with new opportunities in the multicore era due to its robustness in application coding and porting across heterogeneous computing platforms. For example, microprogramming may be a feasible approach in the realm of cloud computing services. However, it increases the energy consumption. The investigation of the opportunities of Microprogramming  should become the focus of a future subcommittee working under the sponsorship of TCuARCH.

 

The above examples are only a few of the areas that require new, exciting efforts in the Microprogramming and Microarchitecture field.

In addition, since many researchers in the embedded computing systems field are moving into the multicore processor arena, a major effort should be made to increase our membership by effectively targeting these researchers.