IEEE Computer Society - Keywords - Hardware
B.0General
B.1Control Structures and Microprogramming
B.1.0General
B.1.1Control Design Styles
B.1.1.aHardwired control
B.1.1.bMicroprogrammed logic arrays
B.1.1.cWritable control store
B.1.2Control Structure Performance Analysis and Design Aids
B.1.2.aAutomatic synthesis
B.1.2.bFormal models
B.1.2.cSimulation
B.1.3Control Structure Reliability, Testing, and Fault-Tolerance
B.1.3.aDiagnostics
B.1.3.bError-checking
B.1.3.cRedundant design
B.1.3.dTest generation
B.1.4Microprogram Design Aids
B.1.4.aFirmware engineering
B.1.4.bLanguages and compilers
B.1.4.cMachine-independent microcode generation
B.1.4.dOptimization
B.1.4.eVerification
B.1.5Microcode Applications
B.1.5.aDirect data manipulation
B.1.5.bFirmware support of operating systems/
instruction sets
B.1.5.cInstruction set interpretation
B.1.5.dPeripheral control
B.1.5.eSpecial-purpose
B.1.mMiscellaneous
B.1.m.aEmerging technologies
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B.2 Arithmetic and Logic Structures
B.2.0General
B.2.1Design Styles
B.2.1.aCalculator
B.2.1.bParallel
B.2.1.cPipeline
B.2.1.dMultiple valued logic
B.2.2Performance Analysis and Design Aids
B.2.2.aSimulation
B.2.2.bVerification
B.2.2.cWorst-case analysis
B.2.3Reliability, Testing, and Fault-Tolerance
B.2.3.aDiagnostics
B.2.3.bError-checking
B.2.3.cRedundant design
B.2.3.dTest generation
B.2.4High-Speed Arithmetic
B.2.4.aAlgorithms
B.2.4.bCost/performance
B.2mMiscellaneous
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B.3Memory Structures
B.3.0General
B.3.1Semiconductor Memories
B.3.1.aDRAM
B.3.1.bROM
B.3.1.cSRAM
B.3.2Design Styles
B.3.2.aAssociative memories
B.3.2.bCache memories
B.3.2.cInterleaved memories
B.3.2.dMass storage
B.3.2.ePrimary memory
B.3.2.fSequential-access memory
B.3.2.gShared memory
B.3.2.hVirtual memory
B.3.3Performance Analysis and Design Aids
B.3.3.aFormal models
B.3.3.bSimulation
B.3.3.cWorst-case analysis
B.3.4Reliability, Testing, and Fault-Tolerance
B.3.4.aDiagnostics
B.3.4.bError-checking
B.3.4.cRedundant design
B.3.4.dTest generation
B.3.m Miscellaneous
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B.4I/O and Data Communications
B.4.0General
B.4.1Data Communications Devices
B.4.1.aProcessors
B.4.1.bReceivers
B.4.1.cTransmitters
B.4.2Input/Output Devices
B.4.2.aChannels and controllers
B.4.2.bData terminals and printers
B.4.2.cImage display
B.4.2.dVoice
B.4.3Interconnections (Subsystems)
B.4.3.aAsynchronous/synchronous operation
B.4.3.bFiber optics
B.4.3.cInterfaces
B.4.3.dParallel I/O
B.4.3.ePhysical structures
B.4.3.fTopology
B.4.3.gWeb technologies
B.4.3.hWireless systems
B.4.4Performance Analysis and Design Aids
B.4.4.aFormal models
B.4.4.bSimulation
B.4.4.cVerification
B.4.4.dWorst-case analysis
B.4.5Reliability, Testing, and Fault-Tolerance
B.4.5.aBuilt-in tests
B.4.5.bDiagnostics
B.4.5.cError-checking
B.4.5.dHardware reliability
B.4.5.eRedundant design
B.4.5.fTest generation
B.4.mMiscellaneous
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B.5Register-Transfer-Level Implementation
B.5.0General
B.5.1Design
B.5.1.aArithmetic and logic units
B.5.1.bControl design
B.5.1.cData-path design
B.5.1.dMemory design
B.5.1.eStyles
B.5.2Design Aids
B.5.2.aAutomatic synthesis
B.5.2.bHardware description languages
B.5.2.cOptimization
B.5.2.dSimulation
B.5.2.eVerification
B.5.3Reliability and Testing
B.5.3.aBuilt-in tests
B.5.3.bError-checking
B.5.3.cRedundant design
B.5.3.dTest generation
B.5.3.eTestability
B.5.mMiscellaneous
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B.6Logic Design
B.6.0General
B.6.1Design Styles
B.6.1.aCellular arrays and automata
B.6.1.bCombinational logic
B.6.1.cLogic arrays
B.6.1.dMemory control and access
B.6.1.eMemory used as logic
B.6.1.fParallel circuits
B.6.1.gSequential circuits
B.6.2Reliability and Testing
B.6.2.aBuilt-in tests
B.6.2.bError-checking
B.6.2.cRedundant design
B.6.2.dTest generation
B.6.2.eTestability
B.6.3Design Aids
B.6.3.aAutomatic synthesis
B.6.3.bHardware description languages
B.6.3.cOptimization
B.6.3.dSimulation
B.6.3.eSwitching theory
B.6.3.fVerification
B.6.mMiscellaneous
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B.7Integrated Circuits
B.7.0General
B.7.1Types and Design Styles
B.7.1.aAdvanced technologies
B.7.1.bAlgorithms implemented in hardware
B.7.1.cGate arrays
B.7.1.dInput/output circuits
B.7.1.eMemory technologies
B.7.1.fMicroprocessors and microcomputers
B.7.1.gNetwork connectivity chips
B.7.1.hStandard cells
B.7.1.iVLSI
B.7.2Design Aids
B.7.2.aGraphics
B.7.2.bLayout
B.7.2.cPlacement and routing
B.7.2.dSimulation
B.7.2.eVerification
B.7.3Reliability and Testing
B.7.3.aBuilt-in tests
B.7.3.bError-checking
B.7.3.cFault injection
B.7.3.dRedundant design
B.7.3.eTest generation
B.7.3.fTestability
B7.mMiscellaneous
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B.8Performance and Reliability
B.8.0General
B.8.1 Reliability, Testing, and Fault-Tolerance
B.8.2 Performance Analysis and Design Aids
B.8.mMiscellaneous
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B.9Power Management
B.9.1Low-power design
B.9.2Energy-aware systems
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B.mMiscellaneous
B.m.aDesign management
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This is an extended version of theACM Computing Classification System
Copyright (c) 2002 ACM, used with permission
