A Stanford University research team sponsored by Semiconductor Research Corp. (SRC) has created templates that can help create 22-nanometer logic and memory devices using directed self-assembly (DSA) techniques. “This is the first time that the critical contact holes have been placed with DSA for standard cell libraries of VLSI chips. The result is a composed pattern of real circuits, not just test structures,” said Stanford professor H.-S. Philip Wong, the project’s lead researcher. This enables higher resolutions and finer features on the wafer than other methods, he added. The researchers use a wafer covered with a block copolymer film and, via conventional lithography, created an irregular pattern that acts as a template and guides the movement of the block copolymer into self-assembled configurations. This ultimately enables the creation of contact holes spaced much more closely on the wafer than conventional lithographic techniques allow, which enables smaller, faster, and more energy-efficient chips. Now, the researchers need to work with electronic-design-automation researchers to develop software and tools that will enable circuit designers to specify where these holes are to be located on the wafer. They published their work in Advanced Materials. (PhysOrg)(Semiconductor Research Corporation @ Business Wire)(Advanced Materials)
