Design & Test Editorial Board |  Editor in Chief
Kwang-Ting (Tim) Cheng is a professor of electrical and computer engineering at the University of California, Santa Barbara. His research interests include VLSI testing, design verification, and multimedia computing. Cheng has a BS in electrical engineering from National Taiwan University, and a PhD in electrical engineering and computer science from the University of California, Berkeley. He is a Fellow of the IEEE.
Contact information: University of California, Santa Barbara, Dept. of Electrical & Computer Eng., Santa Barbara, CA 93106-9560; Phone: +1 805 893-7294; Fax: +1 805 893-3262 | Editor in Chief Emeritus
Departments: CEDA Currents
Rajesh Gupta
|  Editor in Chief Emeritus,
Departments: Conference Reports, Panel Summaries, Perspectives
D&T Alliance Program Chair
Yervant Zorian is vice president and chief scientist of Virage Logic, and chief technology advisor of LogicVision. His research interests include developing embedded test and repair strategies for IP cores, chips, and systems. Zorian has an MSc in computer engineering from the University of Southern California and a PhD in electrical engineering from McGill University. He is a Golden Core Member of the IEEE Computer Society, an honorary doctor of the National Academy of Sciences of Armenia, and a Fellow of the IEEE |  Associate EIC
Technical Area: Economics of Design and Test
Magdy Abadir manages the High Performance Tools and Methodology Group at Motorola's PowerPC Design Center in Austin, Texas. He is also an adjunct faculty member of the Computer Engineering Department at the University of Texas at Austin. His research interests include microprocessor test and verification, test economics, EDA tools, and design for test. Abadir has a BS in computer science from the University of Alexandria, Egypt; an MS in computer science from the University of Saskatchewan, Saskatoon, Canada; and a PhD in electrical engineering from the University of Southern California. He is a senior member of the IEEE. |
Technical Areas/Departments/D&T Alliance Program |  Department: Standards
Victor Berman is president and CEO of Improv Systems, a supplier of advanced configurable IP for use in consumer products. His interests include EDA standards, IP, and computer industry in management, sales, and design. His formal training is in language design and electrical engineering in the interdisciplinary Computer Science graduate program at Carnegie Mellon University. This training was put to good use when he headed the team that developed the VHDL language and the first suite of tools to support it. Since then he has managed large development teams including the Verilog-XL team at Cadence. |  Technical Area: Emerging Devices
Krishnendu Chakrabarty is a professor of electrical and computer engineering at Duke University. His research interests include VLSI testing, microfluidic biochips, and wireless sensor networks. Chakrabarty has a BTech from the Indian Institute of Technology, Kharagpur, and an MSE and a PhD from the University of Michigan, all in computer science and engineering. He is a Fellow of IEEE and a senior member of the ACM. |  D&T Alliance Program: Europe
Bernard Courtois is director of the Techniques of Informatics and Microelectronics for Computer Architecture (TIMA) Laboratory and of CMP Service. His research interests include CAD, and architecture and testing of integrated circuits and systems. Courtois has an Engineer degree from the Ecole Nationale Supérieure d'Informatique et Mathématiques Appliquées de Grenoble, and the Docteur-Ingénieur and Docteur-ès-Sciences degrees from the Institut National Polytechnique de Grenoble, France. He is a Golden Core member of the IEEE Computer Society and a member of the ACM, ASME, IEEE, and IMAPS. |  Department: DATC Newsletter
D&T Alliance Program: DATC
Joe Damore is an independent consultant and a member of the Computer Information Systems adjunct faculty at Dutchess Community College in Poughkeepsie, NY. His research interests span all facets of EDA, including hardware and software platforms and languages for developing and executing EDA programs. Damore has a BSEE in electronics from Manhattan College, Riverdale, NY; and an MS in industrial administration from Union College, Schenectady, NY. He is a member of the IEEE, ACM, IEEE Computer Society, and the DATC Executive Committee, and is editor of the DATC Newsletter. |  Departments: The Last Byte, Book Reviews
Scott Davidson is senior staff engineer at Sun Microsystems. His research interests include system test and design for testability. Davidson has a BS from MIT, an MS from the University of Illinois at Urbana-Champaign, and a PhD from the University of Southwestern Louisiana, all in computer science. He is a member of the IEEE. |  Technical Area: Design for Manufacturing, Yield, and Yield Analysis
Dimitris Gizopoulos is an assistant professor in the Department of Informatics at the University of Piraeus, Greece. His research interests include self-testing of embedded processors, processor-based testing of SoC architectures, low-power testing, fault tolerance, and on-line testing. Gizopoulos has a PhD in computer science from the University of Athens, Greece. He is a member of the IEEE and a Golden Core member of the IEEE Computer Society. | | |  Technical Area: SoC Design
Soha Hassoun is an assistant professor in the Department of Computer Science at Tufts University. Her research interests include CAD, VLSI design, and computer architecture. Hassoun has a BS in electrical engineering from South Dakota State University, an MS in electrical engineering from the Massachusetts Institute of Technology, and a PhD in computer science and engineering from the University of Washington, Seattle. She is a member of the ACM, a senior member of the IEEE, and a Fellow of Tau Beta Pi. |  Technical Area: CAE/CAD
Dwight Hill is a principle engineer in the physical synthesis department at Synopsys. His research interests include timing constraint analysis and timing closure, VLSI layout synthesis, interactive CAD systems, and field-programmable gate arrays. Hill has a BS in computer engineering from the University of Illinois, and an MS and a PhD in electrical engineering from Stanford University. He is a senior member of the IEEE. |  Technical Area: Design Validation and Debugging
Michael Hsiao is a professor and dean's faculty fellow in the Bradley Department of Electrical and Computer Engineering at Virginia Tech. His research interests include architectural level and gate level automatic test pattern generation (ATPG), design verification and diagnosis, fault simulation and defect coverage evaluation, design for testability, test set compaction, power estimation and management in VLSI, computer architecture, parallelization, and reliability. He has a PhD and MS in electrical engineering from the University of Illinois at Urbana-Champaign. He is a senior member of the IEEE. |  Technical Area: Infrastructure IP
D&T Alliance Program: TTTC
André Ivanov is a professor in the Department of Electrical and Computer Engineering at the University of British Columbia, Vancouver, Canada; and is a founding director of Vector 12 Corp. His research interests include IC testing; DFT; BIST for digital, analog, and mixed-signal circuits; design and methodologies of large and complex ICs; and SoC technology. Ivanov has a BEng, MEng, and PhD in electrical engineering from McGill University, Montreal, Canada. He is the first vice chair of the Test Technology Technical Council (TTTC) and chair of the TTTC Technical Activities Committees, a Fellow of the British Columbia Advanced Systems Institute, and a senior member of the IEEE. |  Technical Area:Multiprocessor SoC
D&T Alliance Program: DATE
Ahmed Amine Jerraya is acting as head of Design Programs for DCIS (advanced Design and System Division) at CEA/LETI (Commissariat à l’énergie atomique/Laboratoire d’électronique et de technologie de l’information). His research interests include SoCs and system-level specification languages. He has coauthored eight books and published more than 200 papers in international conferences and journals. Jerraya has a Dr Ing in computer sciences from the University of Grenoble, France. |  Department: Roundtables
William H. Joyner Jr. is on assignment from IBM as director of computer-aided design and test at the Semiconductor Research Corp. His research interests include software and hardware verification, logic synthesis and simulation, and physical design. Joyner is past chair of the Design Automation Conference. He has a BS in engineering science from the University of Virginia and a PhD in applied mathematics from Harvard University. He is a fellow of the IEEE. |  Department: The Road Ahead
D&T Alliance Program: DAC
Andrew B. Kahng is a professor in the departments of Computer Science and Engineering and Electrical and Computer Engineering of the University of California, San Diego. He also leads the Calibrating Achievable Design activity, which includes the Bookshelf project, in the Marco Gigascale Silicon Research Center. His research interests include VLSI physical layout design and performance analysis, combinatorial and graph algorithms, and large-scale heuristic global optimization. Kahng has an AB in applied mathematics (physics) from Harvard College and an MS and a PhD, both in computer science, from the University of California, San Diego. He is a member of the IEEE and the ACM. |  Technical Area: Microelectronic IC Packaging
Bruce Kim is an associate professor in the Department of Electrical and Computer Engineering of the University of Alabama. His research interests include micro and nanosystems for RF and biological applications; mixed-signal and RF IC design; microelectronics IC packaging; VLSI design and verification; and VLSI algorithms and CAD. Kim has a BS in electrical engineering from the University of California, Irvine; an MS in electrical engineering from the University of Arizona; and a Ph.D. in electrical and computer engineering from the Georgia Institute of Technology. He is a senior member of the IEEE. |  Technical Area: Logic and Physical Synthesis
David Kung is the Senior Manager of the Design Automation Department in IBM Research and is responsible for the Design Automation research strategy. His research interests are in all areas of CAD, with main focus in the area of logic and physical synthesis. He received a BA in Physics from U.C. Berkeley, M.A. in Physics from Harvard, and a PhD in Physics from Stanford University. He is a senior member of the IEEE. |  Technical Area: Configurable Computing
Fadi Kurdahi
D&T Alliance Program: DAC
Luciano Lavagno
|  Technical Area: Memory Test
Fabrizio Lombardi chairs the Department of Electrical and Computer Engineering at Northeastern University, Boston, where he also holds the International Test Conference Endowed Professorship. His research interests include testing and design of digital systems, ATE systems, configurable and network computing, defect tolerance, and CAD for VLSI. Lombardi has a BSc in electronic engineering from the University of Essex, UK; and an MS in microwaves and modern optics and a Diploma in microwave engineering, both from University College London. He is the associate editor in chief of the IEEE Transactions on Computers and the founding general chair of the IEEE Symposium on Network Computing and Applications. | | |  Technical Area: SoC Testing
Erik Jan Marinissen is a Principal Scientist at IMEC in Leuven, Belgium. Previously, he worked at NXP Semiconductors and Philips Research in Eindhoven, The Netherlands. His research interests include all aspects of integrated circuit testing and design-for-test. Marinissen holds an MSc in Computing Science and a PDEng degree in Software Technology, both from Eindhoven University of Technology, The Netherlands.He is a Senior Member of IEEE and Golden Core Member of the Computer Society.
Department: Book Reviews
Igor Markov Technical Area: Design Reuse
Department: Book Reviews
Grant Martin |  Technical Area: Deep-Submicron IC
Design and Analysis
Sani Nassif is the manager of the Tools and Technology department at the IBM Austin Research Laboratory. As such, he oversees research in CAD, computer-aided verification, testing, design for manufacturability, and thermoelectric cooling. The CAD work includes transistor-level simulation, analysis, and optimization (sizing); algorithms for placement, buffer insertion, and wire and buffer sizing; and power grid analysis. Dr. Nassif has a BA in electrical engineering from the American University of Beirut, and an MS and a PhD in electrical and computer engineering from Carnegie Mellon University. He is a senior member of the IEEE. | Technical Area: Defect and Fault Tolerance
Michael Nicolaidis is the research director of the CNRS (French National Research Center) and chief technical officer of iRoC Technologies. His research interests include VLSI testing, DFT, online testing, fault tolerant design, reliability issues in very deep-submicron technologies, fault tolerant approaches for nanotechnologies, fundamental physics, and philosophy. Dr. Nicolaidis has an EE degree from the University of Thessaloniki, Greece; and the Engineer Doctorate Thesis from the National Polytechnic Institute of Grenoble, France. He is a Golden Core member of the IEEE Computer Society. |  D&T Alliance Program: Asia
Hidetoshi Onodera is a professor in the Department of Communications and Computer Engineering at Kyoto University, Japan. His research interests include EDA and design methods for digital/analog/RF circuits, design for high speed and low power, and design for manufacturability. Onodera has a BE, an ME, and a DEng, all in electronic engineering, from Kyoto University. He is a member of the IEEE, the ACM, IEICE Japan, and IPS Japan. |  Technical Area: Design Verification and Validation
Carl Pixley is a senior director in Synopsys' Advanced Technology Group. His scientific and engineering inventions include the Pixley-Roy topology, the Eaton-Pixley-Edwards-Miller theorem, and the BDD-based approach to model checking, sequential equivalence, resetability, and constraint-based verification. Pixley has a BS, MS, and PhD in mathematics from the University of Omaha, Rutgers University, and SUNY-Binghamton University, respectively. He is a member of the IEEE and the Mathematics Association of America, and has served on the program committees of several IEEE conferences. |  Technical Area: Low Power
Anand Raghunathan is a senior research staff member at NEC Laboratories. His research interests include SoC architectures, design methodologies, and design tools, with an emphasis on high-performance, low-power, and testable designs. Raghunathan has a Btech in electrical and electronics engineering from the Indian Institute of Technology, Madras, India; and an MA and PhD in electrical engineering from Princeton University. He is a senior member of the IEEE, a member of the VLSI Test Symposium organizing committee, and vice chair of the Test Technology Technical Council's Tutorials & Education Group. |  D&T Alliance Program: Latin America
Ricardo Reis is a professor of microelectronics and computer engineering at the Universidade Federal do Rio Grande do Sul, at Porto Alegre, Brazil. His main research interests include physical design, VLSI design and design automation. Reis has an electrical engineering diploma from Universidade Federal do Rio Grande do Sul, and a PhD computer science, option microelectronics from the Institut National Polytechnique de Grenoble, France. He is a Senior Member of the IEEE. He is also member of ACM, SBC and SBMicro. |  Technical Area: Analog and Mixed-Signal Test
Michel Renovell heads the Microelectronics Department at LIRMM. His research interests include fault modeling, analog testing, and FPGA testing. Renovell has a PhD in electrical testing from the University of Montpellier. |  Member at Large
Kaushik Roy is an associate professor of electrical and computer engineering at Purdue University and a Purdue University Faculty Scholar Professor. His research interests include VLSI testing and verification, reconfigurable computing, and VLSI design and CAD with emphasis on low-power electronics for portable computing and wireless communications. Roy has a BTech in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, and a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He is a senior member of the IEEE. |  Department: Perspectives
Alberto Sangiovanni-Vincentelli holds the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California, Berkeley. His research interests include design tools and methodologies, large-scale systems, embedded controllers, and hybrid systems. Sangiovanni-Vincentelli has a DrIng in electrical engineering and computer science from Politecnico di Milano, Italy. He is a cofounder of Cadence and Synopsys, an IEEE Fellow, and a member of the National Academy of Engineering.
Technical Area: Performance Issues in IC Design
Sachin Sapatnekar |  Technical Area: System Specification and Modeling
Sandeep Shukla is an assistant professor of electrical and computer engineering at Virginia Tech, where he also serves as deputy director of the Center for Embedded Systems for Critical Applications (CESCA). His research interests include formal methods and verification, computer architecture, embedded systems design, low-power design methodologies, semantic foundations of design languages, high-level modeling and synthesis, software engineering, and defect-tolerant computing for nanotechnology. Dr. Shukla has a BE in computer science and engineering from Jadavpur University (Calcutta, India), and an MS and PhD in computer science from State University of New York at Albany. He is a senior member of the IEEE. | Technical Area: Defect-Based Test
Adit Singh | | |  Department: TTTC Newsletter
Mohammad Tehranipoor | Department: Interviews
Ken Wagner is manager of PMC-Sierra's Ottawa Design Center. His research interests include low-power design, synchronous design, SoC integration, design for test, and EDA development. Wagner received his MSEE and PhD in electrical engineering from Stanford University. He is a member of the IEEE CAS Society and a Golden Core member of the IEEE Computer Society. |  Technical Area: Embedded Test
Cheng-Wen Wu is a professor of electrical engineering at National Tsing Hua University, Hsinchu, Taiwan. His research interests include VLSI design and testing and memory testing. Wu has a BS in electrical engineering from National Taiwan University, and an MS and a PhD in electrical and computer engineering from the University of California, Santa Barbara. He is a life member of the IC Design Society of Taiwan, a Golden Core member of the IEEE Computer Society, and a Fellow of the IEEE. |
Advisory Board | | Anthony Ambler | | Ivo Bolsens |  Bill Mann is the founder and general chair of the Southwest Test Workshop. He retired in 1998 as the executive director of quality, test, and product engineering at Rockwell Semiconductor Systems. His research interests include wafer-level testing, probe cards and ATE interface, product quality level and test coverage, reliability improvement, outlier rejects, stress testing, final test fixturing, sockets, burn-in-home built ATE, high-volume production testing, and cost of test. Mann has a BS and MS in electrical engineering from the University of California at Santa Barbara. He is an associate editor of IEEE Design & Test, a senior member of the IEEE, and a member of the Test Technology Technical Council and ITC Program Committee. |  Tom Williams is an adjunct professor at the University of Colorado at Boulder. He is also a Synopsys Fellow, a distinction acknowledging the contributions he has brought to the company. His research interests include DFT (scan design and self-test), test generation, fault simulation, synthesis, and fault-tolerant computing. Williams has a BSEE from Clarkson University, an MA in pure mathematics from the State University of New York at Binghamton, and a PhD in electrical engineering from Colorado State University. He is a member of the IEEE and the ACM. | | Yervant Zorian |
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