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ABSTRACT
Excessive switching activity during scan operations endangers the reliability of the chip under test. We propose an architectural solution, which we refer to as Expedited-Compact, to mitigate the scan power problem that otherwise creates high heat dissipation and possibly hot spots. Expedited-Compact architecture advances the response compaction operations by utilizing scan chains as buffer. This enables the flushing of the transition-wise costly response data out of the system quickly, providing scan-out power savings. The proposed DfT-based approach is non-intrusive for design flow, requires a very minor investment in area, and in turn delivers significant and predictable savings in test power. The proposed solution reduces average test power without resorting to x-filling, enabling the application of orthogonal x-filling techniques in conjunction.
INDEX TERMS
response compaction, Test power, scan power, shift power, test compression
CITATION
"Expedited-Compact Architecture for Average Scan Power Reduction", IEEE Design & Test of Computers, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/MDT.2012.2213793
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