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Issue No.05 - September-October (2007 vol.24)
pp: 476-485
Janusz Rajski , Mentor Graphics
Grzegorz Mrugalski , Mentor Graphics
Nilanjan Mukherjee , Mentor Graphics
Mark Kassab , Mentor Graphics
Wu-Tung Cheng , Mentor Graphics
Manish Sharma , Mentor Graphics
Liyang Lai , Mentor Graphics
ABSTRACT
This article presents a two-stage test response compactor with scan selection logic and an on-chip compare-and-response collector. This compactor is capable of handling a wide range of X state profiles, offers compression far higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution.
INDEX TERMS
DFT, embedded test, fault diagnosis, on-chip collection of test data, scan-based designs, selective compaction of test responses
CITATION
Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai, "X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis", IEEE Design & Test of Computers, vol.24, no. 5, pp. 476-485, September-October 2007, doi:10.1109/MDT.2007.177
REFERENCES
4761. S. Mitra, S.S. Lumetta, and M. Mitzenmacher, "X-Tolerant Signature Analysis," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 432–441.
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