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Maintaining I/O Data Coherence in Embedded Multicore Systems
May/June 2009 (vol. 29 no. 3)
pp. 10-19
ASCII Text
x 
 
Thomas B. Berg, "Maintaining I/O Data Coherence in Embedded Multicore Systems," IEEE Micro, vol. 29, no. 3, pp. 10-19, May/June, 2009.
 
 
BibTex
x
 
@article{ 10.1109/MM.2009.44,
author = {Thomas B. Berg},
title = {Maintaining I/O Data Coherence in Embedded Multicore Systems},
journal ={IEEE Micro},
volume = {29},
number = {3},
issn = {0272-1732},
year = {2009},
pages = {10-19},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2009.44},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Maintaining I/O Data Coherence in Embedded Multicore Systems
IS - 3
SN - 0272-1732
SP10
EP19
EPD - 10-19
A1 - Thomas B. Berg,
PY - 2009
KW - multicore
KW - I/O coherence
KW - hardware/software interfaces
KW - memory hierarchy
KW - embedded systems
KW - coherence manager
KW - cache
VL - 29
JA - IEEE Micro
ER -
 
Thomas B. Berg, MIPS Technologies

In embedded systems, multiple cores mean multiple caches and often multiple cache levels. Consequently, maintaining coherency between the cores' caches and the data generated or consumed by I/O devices is challenging, with different solutions trading off hardware versus software complexity. The optimal approach for I/O data coherence depends on application and system characteristics, and might require a combination of techniques.

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Index Terms:
multicore, I/O coherence, hardware/software interfaces, memory hierarchy, embedded systems, coherence manager, cache
Citation:
Thomas B. Berg, "Maintaining I/O Data Coherence in Embedded Multicore Systems," IEEE Micro, vol. 29, no. 3, pp. 10-19, May-June 2009, doi:10.1109/MM.2009.44
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