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International Symposium on Code Generation and Optimization (CGO'04)
Improving 64-Bit Java IPF Performance by Compressing Heap References
San Jose, California
March 20-March 24
ISBN: 0-7695-2102-9
Ali-Reza Adl-Tabatabai, Intel Corporation
Jay Bharadwaj, Intel Corporation
Michal Cierniak, Microsoft Corporation
Marsha Eng, Intel Corporation
Jesse Fang, Intel Corporation
Brian T. Lewis, Intel Corporation
Brian R. Murphy, Intel Corporation
James M. Stichnoth, Intel Corporation
64-bit processor architectures like the Intel? Itanium? Processor Family are designed for large applications that need large memory addresses. When running applications that fit within a 32-bit address space, 64-bit CPUs are at a disadvantage compared to 32-bit CPUs because of the larger memory footprints for their data. This results in worse cache and TLB utilization, and consequently lower performance because of increased miss ratios. This paper considers software techniques for virtual machines that allow 32-bit pointers to be used on 64-bit CPUs for managed runtime applications that do not need the full 64-bit address space. We describe our pointer compression techniques and discuss our experience implementating these for Java1 applications. In addition, we give performance results with our techniques for both the SPEC JVM98 and SPEC JBB2000 benchmarks. We demonstrate a 12% performance improvement on SPEC JBB2000 and a reduction in the number of garbage collections required for a given heap size.
Ali-Reza Adl-Tabatabai, Jay Bharadwaj, Michal Cierniak, Marsha Eng, Jesse Fang, Brian T. Lewis, Brian R. Murphy, James M. Stichnoth, "Improving 64-Bit Java IPF Performance by Compressing Heap References," cgo, pp.100, International Symposium on Code Generation and Optimization (CGO'04), 2004
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