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IEEE Workshop on Software Technologies for Future Embedded Systems
Formal Probabilistic Refinement Verification of Embedded Real-Time Systems
Hakodate, Hokkaido, Japan
May 15-May 16
ISBN: 0-7695-1937-7
ASCII Text
x 
 
Satoshi Yamane, "Formal Probabilistic Refinement Verification of Embedded Real-Time Systems," Software Technologies for Future Embedded Systems, IEEE Workshop on, pp. 79, IEEE Workshop on Software Technologies for Future Embedded Systems, 2003.
 
 
BibTex
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@article{ 10.1109/WSTFES.2003.1201366,
author = {Satoshi Yamane},
title = {Formal Probabilistic Refinement Verification of Embedded Real-Time Systems},
journal ={Software Technologies for Future Embedded Systems, IEEE Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-1937-7},
pages = {79},
doi = {http://doi.ieeecomputersociety.org/10.1109/WSTFES.2003.1201366},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Software Technologies for Future Embedded Systems, IEEE Workshop on
TI - Formal Probabilistic Refinement Verification of Embedded Real-Time Systems
SN - 0-7695-1937-7
SP
EP
A1 - Satoshi Yamane,
PY - 2003
KW - null
VL - 0
JA - Software Technologies for Future Embedded Systems, IEEE Workshop on
ER -
 
Satoshi Yamane, Kanazawa University
Generally, real-time systems have been specified using timed automata, and moreover model-checking methods of timed automata have been developed. On the other hand, recently, probabilistic timed automata have been developed in order to express the relative likelihood of the system exhibiting certain behavior. In this paper, we develop the verification method of simulation relation of probabilistic timed automata, and apply this method into stepwise refinement developments of real-time systems.
Citation:
Satoshi Yamane, "Formal Probabilistic Refinement Verification of Embedded Real-Time Systems," wstfes, pp.79, IEEE Workshop on Software Technologies for Future Embedded Systems, 2003
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