ARAS: asynchronous RISC architecture simulator

A
ASYNC
1995
Second Working Conference on Asynchronous Design Methodologies
Abstract - ARAS: asynchronous RISC architecture simulator

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Second Working Conference on Asynchronous Design Methodologies

London, England

May 30-May 31

ISBN: 0-8186-7098-3

	ASCII Text	x
	Chia-Hsing Chien, M.A. Franklin, Tienyo Pan, P. Prabhu, "ARAS: asynchronous RISC architecture simulator," Asynchronous Circuits and Systems, International Symposium on, pp. 210, Second Working Conference on Asynchronous Design Methodologies, 1995.

	BibTex	x
	@article{ 10.1109/WCADM.1995.514658, author = {Chia-Hsing Chien and M.A. Franklin and Tienyo Pan and P. Prabhu}, title = {ARAS: asynchronous RISC architecture simulator}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7098-3}, pages = {210}, doi = {http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514658}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - ARAS: asynchronous RISC architecture simulator SN - 0-8186-7098-3 SP EP A1 - Chia-Hsing Chien, A1 - M.A. Franklin, A1 - Tienyo Pan, A1 - P. Prabhu, PY - 1995 KW - pipeline processing; parallel architectures; virtual machines; performance evaluation; asynchronous RISC architecture simulator; ARAS; pipeline instruction simulator; performance measurements; benchmark programs; pipeline configuration; asynchronous pipeline architectures VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Chia-Hsing Chien, Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

M.A. Franklin, Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

Tienyo Pan, Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

P. Prabhu, Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514658

In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this simulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline configuration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, the pipeline configuration can be altered to improve its performance. Thus, one can explore the design space of asynchronous pipeline architectures.

Index Terms:

pipeline processing; parallel architectures; virtual machines; performance evaluation; asynchronous RISC architecture simulator; ARAS; pipeline instruction simulator; performance measurements; benchmark programs; pipeline configuration; asynchronous pipeline architectures

Citation:

Chia-Hsing Chien, M.A. Franklin, Tienyo Pan, P. Prabhu, "ARAS: asynchronous RISC architecture simulator," async, pp.210, Second Working Conference on Asynchronous Design Methodologies, 1995

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