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Second Working Conference on Asynchronous Design Methodologies
Hierarchical gate-level verification of speed-independent circuits
London, England
May 30-May 31
ISBN: 0-8186-7098-3
ASCII Text
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O. Roig, J. Cortadella, E. Pastor, "Hierarchical gate-level verification of speed-independent circuits," Asynchronous Circuits and Systems, International Symposium on, pp. 128, Second Working Conference on Asynchronous Design Methodologies, 1995.
 
 
BibTex
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@article{ 10.1109/WCADM.1995.514650,
author = {O. Roig and J. Cortadella and E. Pastor},
title = {Hierarchical gate-level verification of speed-independent circuits},
journal ={Asynchronous Circuits and Systems, International Symposium on},
volume = {0},
year = {1995},
isbn = {0-8186-7098-3},
pages = {128},
doi = {http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514650},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asynchronous Circuits and Systems, International Symposium on
TI - Hierarchical gate-level verification of speed-independent circuits
SN - 0-8186-7098-3
SP
EP
A1 - O. Roig,
A1 - J. Cortadella,
A1 - E. Pastor,
PY - 1995
KW - asynchronous circuits; logic testing; computational complexity; hierarchical gate-level verification; speed-independent circuits; complex gates; time complexity; state signals
VL - 0
JA - Asynchronous Circuits and Systems, International Symposium on
ER -
 
O. Roig, Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Cortadella, Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain
E. Pastor, Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain
This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.
Index Terms:
asynchronous circuits; logic testing; computational complexity; hierarchical gate-level verification; speed-independent circuits; complex gates; time complexity; state signals
Citation:
O. Roig, J. Cortadella, E. Pastor, "Hierarchical gate-level verification of speed-independent circuits," async, pp.128, Second Working Conference on Asynchronous Design Methodologies, 1995
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