Second Working Conference on Asynchronous Design Methodologies A single-rail re-implementation of a DCC error detector using a generic standard-cell library London, England May 30-May 31 ISBN: 0-8186-7098-3
We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.
Index Terms:
digital audio tape; error detection codes; asynchronous circuits; cellular arrays; integrated logic circuits; high level synthesis; DCC error detector; generic standard-cell library; single-rail re-implementation; fully asynchronous implementation; handshake signaling; single-rail data encoding; generic cell library; high-level Tangram description; handshake circuits; intermediate architecture; power dissipation
Citation:
K. Van Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, F. Schalij, R. van de Wiel, "A single-rail re-implementation of a DCC error detector using a generic standard-cell library," async, pp.72, Second Working Conference on Asynchronous Design Methodologies, 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||