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Second Working Conference on Asynchronous Design Methodologies
High-level test evaluation of asynchronous circuits
London, England
May 30-May 31
ISBN: 0-8186-7098-3
ASCII Text
x 
 
R. van de Wiel, "High-level test evaluation of asynchronous circuits," Asynchronous Circuits and Systems, International Symposium on, pp. 63, Second Working Conference on Asynchronous Design Methodologies, 1995.
 
 
BibTex
x
 
@article{ 10.1109/WCADM.1995.514643,
author = {R. van de Wiel},
title = {High-level test evaluation of asynchronous circuits},
journal ={Asynchronous Circuits and Systems, International Symposium on},
volume = {0},
year = {1995},
isbn = {0-8186-7098-3},
pages = {63},
doi = {http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514643},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asynchronous Circuits and Systems, International Symposium on
TI - High-level test evaluation of asynchronous circuits
SN - 0-8186-7098-3
SP
EP
A1 - R. van de Wiel,
PY - 1995
KW - asynchronous circuits; logic testing; VLSI; error detection codes; asynchronous circuits; high-level test evaluation; production fault tests; fault model; high-level circuit description; asynchronous 22 k transistor DCC error corrector IC
VL - 0
JA - Asynchronous Circuits and Systems, International Symposium on
ER -
 
R. van de Wiel, Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands
The present a method for evaluating production fault tests for asynchronous circuits. A novel fault model is defined, based on a high-level circuit description, allowing the evaluation of production tests on the design level. This evaluation method is used in the test generation for an asynchronous 22 k transistor DCC error corrector IC, resulting in a fault coverage of 99.8%.
Index Terms:
asynchronous circuits; logic testing; VLSI; error detection codes; asynchronous circuits; high-level test evaluation; production fault tests; fault model; high-level circuit description; asynchronous 22 k transistor DCC error corrector IC
Citation:
R. van de Wiel, "High-level test evaluation of asynchronous circuits," async, pp.63, Second Working Conference on Asynchronous Design Methodologies, 1995
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