New CMOS VLSI linear self-timed architectures

A
ASYNC
1995
Second Working Conference on Asynchronous Design Methodologies
Abstract - New CMOS VLSI linear self-timed architectures

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	Similar Articles Articles by A.J. Acosta Articles by M. Bellido Articles by M. Valencia Articles by A. Barriga Articles by R. Jimenez Articles by J.L. Huertas

Second Working Conference on Asynchronous Design Methodologies

London, England

May 30-May 31

ISBN: 0-8186-7098-3

	ASCII Text	x
	A.J. Acosta, M. Bellido, M. Valencia, A. Barriga, R. Jimenez, J.L. Huertas, "New CMOS VLSI linear self-timed architectures," Asynchronous Circuits and Systems, International Symposium on, pp. 14, Second Working Conference on Asynchronous Design Methodologies, 1995.

	BibTex	x
	@article{ 10.1109/WCADM.1995.514638, author = {A.J. Acosta and M. Bellido and M. Valencia and A. Barriga and R. Jimenez and J.L. Huertas}, title = {New CMOS VLSI linear self-timed architectures}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7098-3}, pages = {14}, doi = {http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514638}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - New CMOS VLSI linear self-timed architectures SN - 0-8186-7098-3 SP EP A1 - A.J. Acosta, A1 - M. Bellido, A1 - M. Valencia, A1 - A. Barriga, A1 - R. Jimenez, A1 - J.L. Huertas, PY - 1995 KW - digital signal processing chips; VLSI; asynchronous circuits; semiconductor storage; CMOS memory circuits; CMOS VLSI linear self-timed architectures; digital signal processor circuits; self-timed techniques; synchronous VLSI circuits; hardware resources; asynchronous circuits; FIFO memories VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

A.J. Acosta, Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

M. Bellido, Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

M. Valencia, Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

A. Barriga, Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

R. Jimenez, Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

J.L. Huertas, Dept. de Diseno de Circuitos Analogicos, Seville Univ., Spain

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514638

The implementation of digital signal processor circuits via self-timed techniques is currently a valid alternative to solve some problems encountered in synchronous VLSI circuits. However, a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously reported linear self-timed architecture, and their application in the design of FIFO memories. Furthermore, the integration and characterization in the laboratory of prototypes of these FIFOs are presented.

Index Terms:

digital signal processing chips; VLSI; asynchronous circuits; semiconductor storage; CMOS memory circuits; CMOS VLSI linear self-timed architectures; digital signal processor circuits; self-timed techniques; synchronous VLSI circuits; hardware resources; asynchronous circuits; FIFO memories

Citation:

A.J. Acosta, M. Bellido, M. Valencia, A. Barriga, R. Jimenez, J.L. Huertas, "New CMOS VLSI linear self-timed architectures," async, pp.14, Second Working Conference on Asynchronous Design Methodologies, 1995

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