22nd International Conference on Advanced Information Networking and Applications - Workshops (aina workshops 2008)
Wireless Sensor Nodes Processor Architecture and Design
March 25-March 28
ISBN: 978-0-7695-3096-3
In this paper, a specialized soft processing core for sensor nodes has been designed and implemented. The paper presents a detailed view of architecture and the instructions set of the processor. The core can be easily integrated with other sensor node parts to construct different types of nodes that can be used to support different sensor network applications. The core is implemented using Xilinx ISE 8.2i design tools. The architecture of the core is simple and can process 10.78 MIPS.
Index Terms:
sensor nodes, Processor, FPGA
Citation:
Ali El Kateeb, Aiyappa Ramesh, L. Azzawi, "Wireless Sensor Nodes Processor Architecture and Design," ainaw, pp.892-897, 22nd International Conference on Advanced Information Networking and Applications - Workshops (aina workshops 2008), 2008