Conventional methods to assess the test data volume (TDV) of logic in system-on-chips (SoCs) use intuitive formulae that are often agnostic of the target automatic test equipment (ATE) hardware or the ATE test program compilation process. In this paper, we first show that such ATE-unaware approaches lead to a significant gap between these estimates and the actual tester memory consumed. We also provide a generic solution to this problem by using statistical regression techniques to build an ATE-aware TDV model that accurately estimates test program memory consumption as a function of the design and test pattern characteristics. We have implemented this methodology using an off-the-shelf regression solver in the context of a production test flow. We show that the estimator can be used to compute TDV with very high accuracy for logic tests of various industrial IPcores and SoCs.