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26th IEEE VLSI Test Symposium (vts 2008)
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems
April 27-May 01
ISBN: 0-7695-3123-7
Time Interleaved A/D Converters (TIADCs)provide an attractive solution to the realization of analogfront ends in high speed communication systems. However,gain mismatch, offset mismatch, and sampling time mismatchbetween time-interleaved channels limit the performanceof TIADCs. This paper presents a low-cost test scheme tomeasure timing mismatch using an undersampling clock. Ourmethod is applicable to an arbitrary number of channels,achieving picosecond resolution with low power consumption.Both simulation and hardware measurements are presented tovalidate the proposed technique.
Index Terms:
Time-Interleaved ADC, Mixed-signal testing, Low-cost test, Timing Mismatch, High speed testing
Citation:
Qingqi Dou, Jacob A. Abraham, "Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems," vts, pp.3-8, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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