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26th IEEE VLSI Test Symposium (vts 2008)
Dynamic Compaction for High Quality Delay Test
April 27-May 01
ISBN: 0-7695-3123-7
ASCII Text
x 
 
Zheng Wang, D.M.H. Walker, "Dynamic Compaction for High Quality Delay Test," VLSI Test Symposium, IEEE, pp. 243-248, 26th IEEE VLSI Test Symposium (vts 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VTS.2008.54,
author = {Zheng Wang and D.M.H. Walker},
title = {Dynamic Compaction for High Quality Delay Test},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2008},
issn = {1093-0167},
pages = {243-248},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2008.54},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Dynamic Compaction for High Quality Delay Test
SN - 1093-0167
SP243
EP248
A1 - Zheng Wang,
A1 - D.M.H. Walker,
PY - 2008
KW - delay test
KW - path delay fault
KW - dynamic compaction
KW - test generation
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Dynamic compaction of K Longest Paths Per Gate (KLPG) test sets is performed, resulting in test sets of similar size to transition fault test sets, but with higher quality.
Index Terms:
delay test, path delay fault, dynamic compaction, test generation
Citation:
Zheng Wang, D.M.H. Walker, "Dynamic Compaction for High Quality Delay Test," vts, pp.243-248, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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