26th IEEE VLSI Test Symposium (vts 2008)
Bounded Adjacent Fill for Low Capture Power Scan Testing
April 27-May 01
ISBN: 0-7695-3123-7
DOI Bookmark:
http://doi.ieeecomputersociety.org/10.1109/VTS.2008.47
Average and peak power dissipation can be reduced by controlling the switching activity in the scan chains during shift and capture cycles. In particular, minimum transition count or adjacent fill algorithm reduces transitions in the scan chains and has been shown to reduce average power dissipation during shift. In this paper, we show via statistical analysis of industrial circuits that contrary to conventional belief, scan-in and scan-out vectors are highly correlated for adjacent fill vectors. We also show that this correlation can be used to control the switching activity during the capture cycle. We propose a new filling algorithm called Bounded Adjacent fill that generates test vectors with low shift and capture switching activity and with no impact on pattern count.
Index Terms:
low power, test, capture power, scan, random fill, shift power
Citation:
Anshuman Chandra, Rohit Kapur, "Bounded Adjacent Fill for Low Capture Power Scan Testing," vts, pp.131-138, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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