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26th IEEE VLSI Test Symposium (vts 2008)
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions
April 27-May 01
ISBN: 0-7695-3123-7
This paper presents an innovative approach for the generation of functional programs to test path-delay faults within microprocessors. The proposed method takes advantage of both the gate- and RT-level description of the processor. The former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is exploited for the automatic generation of test programs able to excite and propagate fault effects, based on an evolutionary algorithm and fast RTL simulation. Experimental results on a simple microcontroller show that the proposed methodology is able to generate suitable test sets in reduced times.
Index Terms:
microprocessor test, SBST, path-delay faults
Citation:
K. Christou, M.K. Michael, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda, "A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions," vts, pp.389-394, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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