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26th IEEE VLSI Test Symposium (vts 2008)
Signature Rollback - A Technique for Testing Robust Circuits
April 27-May 01
ISBN: 0-7695-3123-7
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a robust design has become mandatory. However, standard structural test procedures still address classical fault models and cannot deal with the non-deterministic behavior caused by parameter variations and other reasons. Chips may be rejected, even if the test reveals only non-critical failures that could be compensated during system operation. This paper introduces a scheme for embedded test, which can distinguish critical permanent and non-critical transient failures for circuits with time redundancy. To minimize both yield loss and the overall test time, the scheme relies on partitioning the test into shorter sessions. If a faulty signature is observed at the end of a session, a rollback is triggered, and this particular session is repeated. An analytical model for the expected overall test time provides guidelines to determine the optimal parameters of the scheme.
Index Terms:
Robust Design, Embedded Test, Time Redundancy, Rollback and Recovery, Test Quality and Reliability
Citation:
Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich, "Signature Rollback - A Technique for Testing Robust Circuits," vts, pp.125-130, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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