We present a fully automated flow to generate test patterns for??interconnect open defects. Both inter-layer opens (open-via defects)??and arbitrary intra-layer opens can be targeted. An aggressor-victim??model used in industry is employed to describe the electrical??behavior of the open defect. The flow is implemented using standard??commercial tools for parameter extraction (PEX) and test generation??(ATPG). A highly optimized branch-and bound algorithm to determine??the values to be assigned to the aggressor lines is used to reduce??both the ATPG efforts and the number of aborts. The resulting test??sets are smaller and achieve a higher defect coverage than stuck-at??n-detection test sets, and are robust against process variations.