26th IEEE VLSI Test Symposium (vts 2008) Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry April 27-May 01 ISBN: 0-7695-3123-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2008.26
In an SRAM array, the systematic inter-die and the random within-die variations in process parameters cause significant number of parametric failures, to degrade process yield in the nanometer technology regime. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures. To improve robustness of SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writability of the cell directly. Computer simulations based on 45nm PD/SOI technology demonstrate the viability and effectiveness of the scheme in SRAM yield enhancement.
Index Terms:
Design, failure, SRAM, variation, yield
Citation:
Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy, "Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry," vts, pp.101-106, 26th IEEE VLSI Test Symposium (vts 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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