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26th IEEE VLSI Test Symposium (vts 2008)
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults
April 27-May 01
ISBN: 0-7695-3123-7
This paper presents a new fault node for implication graph that represents the Boolean detectability status of afault in the circuit. An implication graph with fault nodes is termed functional fault graph (FFG) because such a graph stores both the functional information and the fault information of the circuit. By computing the transitive closure and graph condensation of the FFG of a circuit, we show that we can collapse faults, and identify untestable faults and independent fault pairs in the circuit. Compared to prior fault independent-based approaches for fault collapsing, our technique gives the best result by reducing the fault-set size by 66%. Additional advantages of our technique compared to previous techniques are: a) It can also identify independent fault pairs in the circuit, and b) It can be extended for other fault models and has a variety of applications. Our experiment with c7552 also found more than 268K independent fault pairs. This work also introduces the first fault-independent polynomial-time approach for identifying untestable transition delay faults.
Index Terms:
Fault Collapsing, Implication Graph, ATPG, Diagnosis, Fault Model
Citation:
Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal, "Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults," vts, pp.329-335, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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