We describe a synthesis-for-testability approach targeting broadside testing of transition faults. We refer to this process as synthesis for broadside testability. Unlike design-for-testability (DFT) procedures that require additional control inputs to implement DFT modes of operation, synthesis for broadside testability uses only the standard scan design and relies on broadside tests to detect target faults. The proposed procedure improves the testability of a circuit by changing next-states of state-transitions from its unreachable states, i.e., states that the circuit cannot enter during functional operation. In this way, it replaces broadside tests of the original circuit with new broadside tests that are more effective in detecting target faults.