24th IEEE VLSI Test Symposium Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking Berkeley, California April 30-May 04 ISBN: 0-7695-2514-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.88
Chip overheating due to excessive and unbalanced power dissipation has become a critical problem during test of complex core-based systems. In this paper, we address the overheating problem in network-on-chip systems by using on-chip multiple-frequency clocking. We control the core temperatures during test scheduling by varying the test clock frequency assigned to each core, so that the power dissipation of each core during test can be adjusted individually and thermal balance is achieved. We present a heuristic where the optimization process can be integrated with test scheduling. Experimental results for NoC benchmarks show that the proposed method can guarantee thermal safety and yield better thermal balance.
Citation:
Chunsheng Liu, Vikram Iyengar, D.K. Pradhan, "Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking," vts, pp.46-51, 24th IEEE VLSI Test Symposium, 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||