loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
24th IEEE VLSI Test Symposium
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
Chunsheng Liu, University of Nebraska-Lincoln
Vikram Iyengar, IBM Microelectronics
D.K. Pradhan, University of Bristol, UK
Chip overheating due to excessive and unbalanced power dissipation has become a critical problem during test of complex core-based systems. In this paper, we address the overheating problem in network-on-chip systems by using on-chip multiple-frequency clocking. We control the core temperatures during test scheduling by varying the test clock frequency assigned to each core, so that the power dissipation of each core during test can be adjusted individually and thermal balance is achieved. We present a heuristic where the optimization process can be integrated with test scheduling. Experimental results for NoC benchmarks show that the proposed method can guarantee thermal safety and yield better thermal balance.
Citation:
Chunsheng Liu, Vikram Iyengar, D.K. Pradhan, "Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking," vts, pp.46-51, 24th IEEE VLSI Test Symposium, 2006
Usage of this product signifies your acceptance of the Terms of Use.