In this paper, we investigate the impacts of the untestable defects, modeled by stuck-open faults and bridging faults, on the quality of transition fault test set. The presence of those defects may make some transition faults to be tested invalidly if they are not considered during transition fault test generation. As a result, the chips with delay defects may escape from testing. Two incremental ATPG procedures are proposed to address invalidly tested transition faults. Experimental results show that the quality of the transition fault test set can be maintained with few additional test patterns.