The Impacts of Untestable Defects on Transition Fault Testing

V
VTS
2006
24th IEEE VLSI Test Symposium
Abstract - The Impacts of Untestable Defects on Transition Fault Testing

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	Similar Articles Articles by Xijiang Lin Articles by Janusz Rajski

24th IEEE VLSI Test Symposium

Berkeley, California

April 30-May 04

ISBN: 0-7695-2514-8

	ASCII Text	x
	Xijiang Lin, Janusz Rajski, "The Impacts of Untestable Defects on Transition Fault Testing," VLSI Test Symposium, IEEE, pp. 2-7, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.87, author = {Xijiang Lin and Janusz Rajski}, title = {The Impacts of Untestable Defects on Transition Fault Testing}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {2-7}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.87}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - The Impacts of Untestable Defects on Transition Fault Testing SN - 0-7695-2514-8 SP2 EP7 A1 - Xijiang Lin, A1 - Janusz Rajski, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Xijiang Lin, Mentor Graphics Corp.

Janusz Rajski, Mentor Graphics Corp.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.87

In this paper, we investigate the impacts of the untestable defects, modeled by stuck-open faults and bridging faults, on the quality of transition fault test set. The presence of those defects may make some transition faults to be tested invalidly if they are not considered during transition fault test generation. As a result, the chips with delay defects may escape from testing. Two incremental ATPG procedures are proposed to address invalidly tested transition faults. Experimental results show that the quality of the transition fault test set can be maintained with few additional test patterns.

Citation:

Xijiang Lin, Janusz Rajski, "The Impacts of Untestable Defects on Transition Fault Testing," vts, pp.2-7, 24th IEEE VLSI Test Symposium, 2006

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