Silicon Evaluation of Logic Proximity Bridge Patterns

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24th IEEE VLSI Test Symposium

Berkeley, California

April 30-May 04

ISBN: 0-7695-2514-8

	ASCII Text	x
	Eric N Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty, "Silicon Evaluation of Logic Proximity Bridge Patterns," VLSI Test Symposium, IEEE, pp. 78-85, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.82, author = {Eric N Tran and Vishwashanth Kasulasrinivas and Sreejit Chakravarty}, title = {Silicon Evaluation of Logic Proximity Bridge Patterns}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {78-85}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.82}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Silicon Evaluation of Logic Proximity Bridge Patterns SN - 0-7695-2514-8 SP78 EP85 A1 - Eric N Tran, A1 - Vishwashanth Kasulasrinivas, A1 - Sreejit Chakravarty, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Eric N Tran, Intel Corporation

Vishwashanth Kasulasrinivas, Intel Corporation

Sreejit Chakravarty, Intel Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.82

Logic Proximity Bridge (LPB) patterns were proposed as an alternative to realistic bridge and ndetect patterns based on simulation studies. Here, silicon evaluation of logic proximity bridge patterns, on a mobile chipset product, is presented. Results show these patterns to significantly increase the class scan fallout above and beyond stuck-at patterns, consisting of single load and multi-load patterns, with very high stuck-at fault coverage. In addition it points to the usefulness of generating ATPG patterns using multiple fault models, LPB faults being one of them.

Citation:

Eric N Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty, "Silicon Evaluation of Logic Proximity Bridge Patterns," vts, pp.78-85, 24th IEEE VLSI Test Symposium, 2006

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