24th IEEE VLSI Test Symposium
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant captureinduced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.
Citation:
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita, "A New ATPG Method for Efficient Capture Power Reduction During Scan Testing," vts, pp.58-65, 24th IEEE VLSI Test Symposium, 2006