Ability to ramp a chip on time is very critical to the success of a product due to short product lifetimes. However, in the nanometer era, shrinking geometries, sub-wavelength lithography, use of new materials (Cu and low-k) and the new processes (CMP) are making this task difficult. Moreover the distribution of the yield loss mechanisms is changing as well. Yield loss is being dominated by the systematic design-process interactions rather than random defects. This renders the learnings from the previous technology nodes inapplicable to the new technology nodes. While the design tools are trying to invent new techniques (e.g. OPC) and new rules (e.g. DFM) to minimize the yield loss, their combined efforts are not suffient to prevent the significant yield loss. Moreover, the design complexities make the application of some of these techniques impractical. Thus it becomes imperative to use real silicon to understand the yield loss mechanisms.