The ITRS roadmap predicts the need for very high testing parallelism to full wafer testing by year 2010. This goal should be achieved with multi-site efficiency well above 90%. This hypothesis put tough requirements on different components of the current concept of test cell. What do we need to achieve these targets? Will the existing and widely adopted contacting technology adequate for that? Will we still be using testers with per pin/site instrumentations? Will the PC be mostly a "passive" piece of hardware? Will we still consider the PC a "consumable"? Which is the economic model behind these new test paradigms? These issues require more discussion. They also require the evaluation of new technologies and why not, to approach differently the partitioning of test resources within the test cell (ATE, probe card, probe station and DUT).