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24th IEEE VLSI Test Symposium
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
ASCII Text
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Ajay Khoche, "Session Abstract," VLSI Test Symposium, IEEE, pp. 152-153, 24th IEEE VLSI Test Symposium, 2006.
 
 
BibTex
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@article{ 10.1109/VTS.2006.73,
author = {Ajay Khoche},
title = {Session Abstract},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2006},
isbn = {0-7695-2514-8},
pages = {152-153},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.73},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Session Abstract
SN - 0-7695-2514-8
SP152
EP153
A1 - Ajay Khoche,
PY - 2006
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Ajay Khoche, Agilent Technologies
Test and verification challenges force industry to explore various partitioning alternatives for the limited test resources. One such alternative involves moving the test instruments inside the chip. This session will present three such solutions where logic analyzer have been embedded in the FPAGs for better observability and reduced design debug times.
Citation:
Ajay Khoche, "Session Abstract," vts, pp.152-153, 24th IEEE VLSI Test Symposium, 2006
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